MCQOPTIONS
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MCQOPTIONS
This section includes 358 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 251. |
Latch is a device with |
| A. | one stable state |
| B. | two stable state |
| C. | three stable state |
| D. | infinite stable states |
| Answer» C. three stable state | |
| 252. |
What is a trigger pulse? |
| A. | a pulse that starts a cycle of operation |
| B. | a pulse that reverses the cycle of operation |
| C. | a pulse that prevents a cycle of operation |
| D. | a pulse that enhances a cycle of operation |
| Answer» B. a pulse that reverses the cycle of operation | |
| 253. |
A latch is an example of a |
| A. | monostable multivibrator |
| B. | astable multivibrator |
| C. | bistable multivibrator |
| D. | 555 timer |
| Answer» D. 555 timer | |
| 254. |
The output of latches will remain in set/reset untill |
| A. | the trigger pulse is given to change the state |
| B. | any pulse given to go into previous state |
| C. | they don’t get any pulse more |
| D. | the pulse is edge-triggered |
| Answer» B. any pulse given to go into previous state | |
| 255. |
In S-R flip-flop, if Q = 0 the output is said to be |
| A. | set |
| B. | reset |
| C. | previous state |
| D. | current state |
| Answer» C. previous state | |
| 256. |
The basic latch consists of |
| A. | two inverters |
| B. | two comparators |
| C. | two amplifiers |
| D. | two adders |
| Answer» B. two comparators | |
| 257. |
The sequential circuit is also called |
| A. | flip-flop |
| B. | latch |
| C. | strobe |
| D. | adder |
| Answer» C. strobe | |
| 258. |
How many types of sequential circuits are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 259. |
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called |
| A. | combinational circuits |
| B. | sequential circuits |
| C. | latches |
| D. | flip-flops |
| Answer» C. latches | |
| 260. |
A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? |
| A. | and or or gates |
| B. | xor or xnor gates |
| C. | nor or nand gates |
| D. | and or nor gates |
| Answer» D. and or nor gates | |
| 261. |
Whose operations are more faster among the following? |
| A. | combinational circuits |
| B. | sequential circuits |
| C. | latches |
| D. | flip-flops |
| Answer» B. sequential circuits | |
| 262. |
Which of the following is correct for a gated D-type flip-flop? |
| A. | the q output is either set or reset as soon as the d input goes high or low |
| B. | the output complement follows the input when enabled |
| C. | only one of the inputs can be high at a time |
| D. | the output toggles if one of the inputs is held high |
| Answer» B. the output complement follows the input when enabled | |
| 263. |
When both inputs of a J-K flip-flop cycle, the output will |
| A. | be invalid |
| B. | change |
| C. | not change |
| D. | toggle |
| Answer» D. toggle | |
| 264. |
The truth table for an S-R flip-flop has how many VALID entries? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 265. |
What is the hold condition of a flip-flop? |
| A. | both s and r inputs activated |
| B. | no active s or r input |
| C. | only s is active |
| D. | only r is active |
| Answer» C. only s is active | |
| 266. |
When is a flip-flop said to be transparent? |
| A. | when the q output is opposite the input |
| B. | when the q output follows the input |
| C. | when you can see through the ic packaging |
| D. | when the q output is complementary of the input |
| Answer» C. when you can see through the ic packaging | |
| 267. |
One example of the use of an S-R flip-flop is as |
| A. | racer |
| B. | stable oscillator |
| C. | binary storage register |
| D. | transition pulse generator |
| Answer» D. transition pulse generator | |
| 268. |
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when |
| A. | the clock pulse is low |
| B. | the clock pulse is high |
| C. | the clock pulse transitions from low to high |
| D. | the clock pulse transitions from high to low |
| Answer» D. the clock pulse transitions from high to low | |
| 269. |
What is one disadvantage of an S-R flip-flop? |
| A. | it has no enable input |
| B. | it has a race condition |
| C. | it has no clock input |
| D. | invalid state |
| Answer» E. | |
| 270. |
The difference between a flip-flop & latch is |
| A. | both are same |
| B. | flip-flop consist of an extra output |
| C. | latches has one input but flip-flop has two |
| D. | latch has two inputs but flip-flop has one |
| Answer» D. latch has two inputs but flip-flop has one | |
| 271. |
The S-R flip flop consist of |
| A. | 4 and gates |
| B. | two additional and gates |
| C. | an additional clock input |
| D. | 3 and gates |
| Answer» C. an additional clock input | |
| 272. |
How many types of flip-flops are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 273. |
A NAND based S’-R’ latch can be converted into S-R latch by placing |
| A. | a d latch at each of its input |
| B. | an inverter at each of its input |
| C. | it can never be converted |
| D. | both a d latch and an inverter at its input |
| Answer» E. | |
| 274. |
In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is |
| A. | no change |
| B. | set |
| C. | reset |
| D. | forbidden |
| Answer» B. set | |
| 275. |
What is an ambiguous condition in a NAND based S’-R’ latch? |
| A. | s’=0, r’=1 |
| B. | s’=1, r’=0 |
| C. | s’=1, r’=1 |
| D. | s’=0, r’=0 |
| Answer» E. | |
| 276. |
Which of the following expressions is in the sum-of-products form? |
| A. | (a + b)(c + d) |
| B. | (a * b)(c * d) |
| C. | a* b *(cd) |
| D. | a * b + c * d |
| Answer» E. | |
| 277. |
Looping on a K-map always results in the elimination of |
| A. | variables within the loop that appear only in their complemented form |
| B. | variables that remain unchanged within the loop |
| C. | variables within the loop that appear in both complemented and uncomplemented form |
| D. | variables within the loop that appear only in their uncomplemented form |
| Answer» D. variables within the loop that appear only in their uncomplemented form | |
| 278. |
Each “1†entry in a K-map square represents: |
| A. | a high for each input truth table condition that produces a high output |
| B. | a high output on the truth table for all low input combinations |
| C. | a low output for all possible high input conditions |
| D. | a don’t care condition for all possible input truth table combinations |
| Answer» B. a high output on the truth table for all low input combinations | |
| 279. |
Each “0†entry in a K-map square represents: |
| A. | a high for each input truth table condition that produces a high output |
| B. | a high output on the truth table for all low input combinations |
| C. | a low output for all possible high input conditions |
| D. | a don’t care condition for all possible input truth table combinations |
| Answer» B. a high output on the truth table for all low input combinations | |
| 280. |
The systematic reduction of logic circuits is accomplished by: |
| A. | symbolic reduction |
| B. | ttl logic |
| C. | using boolean algebra |
| D. | using a truth table |
| Answer» D. using a truth table | |
| 281. |
The Boolean expression Y = (AB)’ is logically equivalent to what single gate? |
| A. | nand |
| B. | nor |
| C. | and |
| D. | or |
| Answer» B. nor | |
| 282. |
Which of the examples below expresses the commutative law of multiplication? |
| A. | a + b = b + a |
| B. | a • b = b + a |
| C. | a • (b • c) = (a • b) • c |
| D. | a • b = b • a |
| Answer» E. | |
| 283. |
Which statement below best describes a Karnaugh map? |
| A. | it is simply a rearranged truth table |
| B. | the karnaugh map eliminates the need for using nand and nor gates |
| C. | variable complements can be eliminated by using karnaugh maps |
| D. | a karnaugh map can be used to replace boolean rules |
| Answer» B. the karnaugh map eliminates the need for using nand and nor gates | |
| 284. |
A TTL gate may operate inadvertently as an |
| A. | digital amplifier |
| B. | analog amplifier |
| C. | inverter |
| D. | regulator |
| Answer» C. inverter | |
| 285. |
Standard TTL circuits operate with a volt power supply. |
| A. | 2 |
| B. | 4 |
| C. | 5 |
| D. | 3 |
| Answer» D. 3 | |
| 286. |
TTL inputs are the emitters of a |
| A. | transistor-transistor logic |
| B. | multiple-emitter transistor |
| C. | resistor-transistor logic |
| D. | diode-transistor logic |
| Answer» C. resistor-transistor logic | |
| 287. |
TTL is a |
| A. | current sinking |
| B. | current sourcing |
| C. | voltage sinking |
| D. | voltage sourcing |
| Answer» B. current sourcing | |
| 288. |
The ancestor to the first personal computers. |
| A. | param 1 |
| B. | satyam 1 |
| C. | kenbak 1 |
| D. | mits altair |
| Answer» D. mits altair | |
| 289. |
The full form of TCTL is |
| A. | transistor-coupled transistor logic |
| B. | transistor-capacitor transistor logic |
| C. | transistor-complemented transistor logic |
| D. | transistor-complementary transistor logic |
| Answer» B. transistor-capacitor transistor logic | |
| 290. |
Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of |
| A. | ecl |
| B. | vecl |
| C. | pecl |
| D. | lecl |
| Answer» D. lecl | |
| 291. |
TTL was invented in 1961 by |
| A. | baker clamp |
| B. | james l. buie |
| C. | chris brown |
| D. | frank wanlass |
| Answer» C. chris brown | |
| 292. |
Transistor–transistor logic (TTL) is a class of digital circuits built from |
| A. | jfet only |
| B. | bipolar junction transistors (bjt) |
| C. | resistors |
| D. | bipolar junction transistors (bjt) and resistors |
| Answer» E. | |
| 293. |
The ECL circuits usually operates with |
| A. | negative voltage |
| B. | positive voltage |
| C. | grounded voltage |
| D. | high voltage |
| Answer» B. positive voltage | |
| 294. |
At the time of invention, an ECL was called as |
| A. | source-coupled logic |
| B. | current mode logic |
| C. | current-steering logic |
| D. | emitter-coupled logic |
| Answer» D. emitter-coupled logic | |
| 295. |
ECL was invented in by |
| A. | 1956, baker clamp |
| B. | 1976, james r. biard |
| C. | 1956, hannon s. yourke |
| D. | 1976, yourke |
| Answer» D. 1976, yourke | |
| 296. |
The equivalent of emitter-coupled logic made out of FETs is called |
| A. | cml |
| B. | scfl |
| C. | fecl |
| D. | efcl |
| Answer» C. fecl | |
| 297. |
The full form of SCFL is |
| A. | source-collector logic |
| B. | source-coupled logic |
| C. | source-complementary logic |
| D. | source cored logic |
| Answer» C. source-complementary logic | |
| 298. |
ECL’s major disadvantage is that |
| A. | it requires more power |
| B. | it’s fanout capability is high |
| C. | it creates more noise |
| D. | it is slow |
| Answer» B. it’s fanout capability is high | |
| 299. |
In ECL the fanout capability is |
| A. | high |
| B. | low |
| C. | zero |
| D. | sometimes high and sometimes low |
| Answer» B. low | |
| 300. |
The ECL behaves as |
| A. | not gate |
| B. | nor gate |
| C. | nand gate |
| D. | and gate |
| Answer» C. nand gate | |