MCQOPTIONS
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MCQOPTIONS
This section includes 358 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 151. |
To store 0 in such a cell, the floating point must be |
| A. | reprogrammed |
| B. | restarted |
| C. | charged |
| D. | power off |
| Answer» D. power off | |
| 152. |
The major disadvantage of RAM is? |
| A. | its access speed is too slow |
| B. | its matrix size is too big |
| C. | it is volatile |
| D. | high power consumption |
| Answer» D. high power consumption | |
| 153. |
The initial values in all the cells of an EPROM is |
| A. | 0 |
| B. | 1 |
| C. | both 0 and 1 |
| D. | alternate 0s and 1s |
| Answer» C. both 0 and 1 | |
| 154. |
The check sum method of testing a ROM |
| A. | allows data errors to be pinpointed to a specific memory location |
| B. | provides a means for locating and correcting data errors in specific memory locations |
| C. | indicates if the data in more than one memory location is incorrect |
| D. | simply indicates that the contents of the rom are incorrect |
| Answer» E. | |
| 155. |
Which of the following describes the action of storing a bit of data in a mask ROM? |
| A. | a 0 is stored by connecting the gate of a mos cell to the address line |
| B. | a 0 is stored in a bipolar cell by shorting the base connection to the address line |
| C. | a 1 is stored by connecting the gate of a mos cell to the address line |
| D. | a 1 is stored in a bipolar cell by opening the base connection to the address line |
| Answer» D. a 1 is stored in a bipolar cell by opening the base connection to the address line | |
| 156. |
EPROM uses an array of |
| A. | p-channel enhancement type mosfet |
| B. | n-channel enhancement type mosfet |
| C. | p-channel depletion type mosfet |
| D. | n-channel depletion type mosfet |
| Answer» C. p-channel depletion type mosfet | |
| 157. |
Address decoding for dynamic memory chip control may also be used for |
| A. | chip selection and address location |
| B. | read and write control |
| C. | controlling refresh circuits |
| D. | memory mapping |
| Answer» B. read and write control | |
| 158. |
The EPROM was invented by |
| A. | wen tsing chow |
| B. | dov frohman |
| C. | luis o brian |
| D. | j p longwell |
| Answer» C. luis o brian | |
| 159. |
The number of logic gates and the way of their interconnections can be classified as |
| A. | logical network |
| B. | system network |
| C. | circuit network |
| D. | gate network |
| Answer» B. system network | |
| 160. |
Complement of F’ gives back |
| A. | f’ |
| B. | f |
| C. | ff |
| D. | ff’ |
| Answer» C. ff | |
| 161. |
The simplified expression of full adder carry is |
| A. | c = xy+xz+yz |
| B. | c = xy+xz |
| C. | c = xy+yz |
| D. | c = x+y+z |
| Answer» B. c = xy+xz | |
| 162. |
Decimal digit in BCD can be represented by |
| A. | 1 input line |
| B. | 2 input lines |
| C. | 3 input lines |
| D. | 4 input lines |
| Answer» E. | |
| 163. |
3 bits full adder contains |
| A. | 3 combinational inputs |
| B. | 4 combinational inputs |
| C. | 6 combinational inputs |
| D. | 8 combinational inputs |
| Answer» E. | |
| 164. |
The addition of two decimal digits in BCD can be done through |
| A. | bcd adder |
| B. | full adder |
| C. | ripple carry adder |
| D. | carry look ahead |
| Answer» B. full adder | |
| 165. |
The output sum of two decimal digits can be represented in |
| A. | gray code |
| B. | excess-3 |
| C. | bcd |
| D. | hexadecimal |
| Answer» D. hexadecimal | |
| 166. |
BCD adder can be constructed with 3 IC packages each of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 5 bits |
| Answer» D. 5 bits | |
| 167. |
29 input circuit will have total of |
| A. | 32 entries |
| B. | 128 entries |
| C. | 256 entries |
| D. | 512 entries |
| Answer» E. | |
| 168. |
The decimal number system represents the decimal number in the form of |
| A. | hexadecimal |
| B. | binary coded |
| C. | octal |
| D. | decimal |
| Answer» C. octal | |
| 169. |
What is a recirculating register? |
| A. | serial out connected to serial in |
| B. | all q outputs connected together |
| C. | a register that can be used over again |
| D. | parallel out connected to parallel in |
| Answer» B. all q outputs connected together | |
| 170. |
How much storage capacity does each stage in a shift register represent? |
| A. | one bit |
| B. | two bits |
| C. | four bits |
| D. | eight bits |
| Answer» B. two bits | |
| 171. |
After two clock pulses, the register contains |
| A. | 10111000 |
| B. | 10110111 |
| C. | 11110000 |
| D. | 11111100 |
| Answer» E. | |
| 172. |
When is it important to use a three-state buffer? |
| A. | when two or more outputs are connected to the same input |
| B. | when all outputs are normally high |
| C. | when all outputs are normally low |
| D. | when two or more outputs are connected to two or more inputs |
| Answer» B. when all outputs are normally high | |
| 173. |
In serial shifting method, data shifting occurs |
| A. | one bit at a time |
| B. | simultaneously |
| C. | two bit at a time |
| D. | four bit at a time |
| Answer» B. simultaneously | |
| 174. |
How many methods of shifting of data are available? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 175. |
A shift register is defined as |
| A. | the register capable of shifting information to another register |
| B. | the register capable of shifting information either to the right or to the left |
| C. | the register capable of shifting information to the right only |
| D. | the register capable of shifting information to the left only |
| Answer» C. the register capable of shifting information to the right only | |
| 176. |
A register that is used to store binary information is called |
| A. | data register |
| B. | binary register |
| C. | shift register |
| D. | d – register |
| Answer» C. shift register | |
| 177. |
Registers capable of shifting in one direction is |
| A. | universal shift register |
| B. | unidirectional shift register |
| C. | unipolar shift register |
| D. | unique shift register |
| Answer» C. unipolar shift register | |
| 178. |
In D register, ‘D’ stands for |
| A. | delay |
| B. | decrement |
| C. | data |
| D. | decay |
| Answer» D. decay | |
| 179. |
The main difference between a register and a counter is |
| A. | a register has no specific sequence of states |
| B. | a counter has no specific sequence of states |
| C. | a register has capability to store one bit of information but counter has n-bit |
| D. | a register counts data |
| Answer» B. a counter has no specific sequence of states | |
| 180. |
How many types of registers are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 181. |
The register is a type of |
| A. | sequential circuit |
| B. | combinational circuit |
| C. | cpu |
| D. | latches |
| Answer» B. combinational circuit | |
| 182. |
A register is defined as |
| A. | the group of latches for storing one bit of information |
| B. | the group of latches for storing n-bit of information |
| C. | the group of flip-flops suitable for storing one bit of information |
| D. | the group of flip-flops suitable for storing binary information |
| Answer» E. | |
| 183. |
The output of a full subtractor is same as |
| A. | half adder |
| B. | full adder |
| C. | half subtractor |
| D. | decoder |
| Answer» C. half subtractor | |
| 184. |
The output of a subtractor is given by (if A, B and X are the inputs). |
| A. | a and b xor x |
| B. | a xor b xor x |
| C. | a or b nor x |
| D. | a nor b xor x |
| Answer» C. a or b nor x | |
| 185. |
The full subtractor can be implemented using |
| A. | two xor and an or gates |
| B. | two half subtractors and an or gate |
| C. | two multiplexers and an and gate |
| D. | two comparators and an and gate |
| Answer» C. two multiplexers and an and gate | |
| 186. |
Full subtractor is used to perform subtraction of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 8 bits |
| Answer» C. 4 bits | |
| 187. |
What does minuend and subtrahend denotes in a subtractor? |
| A. | their corresponding bits of input |
| B. | its outputs |
| C. | its inputs |
| D. | borrow bits |
| Answer» D. borrow bits | |
| 188. |
Let A and B is the input of a subtractor then the borrow will be |
| A. | a and b’ |
| B. | a’ and b |
| C. | a or b |
| D. | a and b |
| Answer» C. a or b | |
| 189. |
Let A and B is the input of a subtractor then the output will be |
| A. | a xor b |
| B. | a and b |
| C. | a or b |
| D. | a exnor b |
| Answer» B. a and b | |
| 190. |
Let the input of a subtractor is A and B then what the output will be if A = B? |
| A. | 0 |
| B. | 1 |
| C. | a |
| D. | b |
| Answer» B. 1 | |
| 191. |
How many outputs are required for the implementation of a subtractor? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 192. |
For subtracting 1 from 0, we use to take a from neighbouring bits. |
| A. | carry |
| B. | borrow |
| C. | input |
| D. | output |
| Answer» C. input | |
| 193. |
If A, B and C are the inputs of a full adder then the sum is given by |
| A. | a and b and c |
| B. | a or b and c |
| C. | a xor b xor c |
| D. | a or b or c |
| Answer» D. a or b or c | |
| 194. |
If A, B and C are the inputs of a full adder then the carry is given by |
| A. | a and b or (a or b) and c |
| B. | a or b or (a and b) c |
| C. | (a and b) or (a and b)c |
| D. | a xor b xor (a xor b) and c |
| Answer» B. a or b or (a and b) c | |
| 195. |
The difference between half adder and full adder is |
| A. | half adder has two inputs while full adder has four inputs |
| B. | half adder has one output while full adder has two outputs |
| C. | half adder has two inputs while full adder has three inputs |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 196. |
Half subtractor is used to perform subtraction of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 5 bits |
| Answer» B. 3 bits | |
| 197. |
If A and B are the inputs of a half adder, the sum is given by |
| A. | a and b |
| B. | a or b |
| C. | a xor b |
| D. | a ex-nor b |
| Answer» D. a ex-nor b | |
| 198. |
Half-adders have a major limitation in that they cannot |
| A. | accept a carry bit from a present stage |
| B. | accept a carry bit from a next stage |
| C. | accept a carry bit from a previous stage |
| D. | accept a carry bit from the following stages |
| Answer» D. accept a carry bit from the following stages | |
| 199. |
If A and B are the inputs of a half adder, the carry is given by |
| A. | a and b |
| B. | a or b |
| C. | a xor b |
| D. | a ex-nor b |
| Answer» B. a or b | |
| 200. |
In which operation carry is obtained? |
| A. | subtraction |
| B. | addition |
| C. | multiplication |
| D. | both addition and subtraction |
| Answer» C. multiplication | |