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MCQOPTIONS
This section includes 358 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 201. |
Total number of inputs in a half adder is |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 1 |
| Answer» B. 3 | |
| 202. |
In parts of the processor, adders are used to calculate |
| A. | addresses |
| B. | table indices |
| C. | increment and decrement operators |
| D. | all of the mentioned |
| Answer» E. | |
| 203. |
How many flip-flops are in the 7475 IC? |
| A. | 2 |
| B. | 1 |
| C. | 4 |
| D. | 8 |
| Answer» D. 8 | |
| 204. |
48 MHz. |
| A. | 10.24 khz |
| B. | 5 khz |
| C. | 30.24 khz |
| D. | 15 khz |
| Answer» C. 30.24 khz | |
| 205. |
What is the significance of the J and K terminals on the J-K flip-flop? |
| A. | there is no known significance in their designations |
| B. | the j represents “jump,†which is how the q output reacts whenever the clock goes high and the j input is also high |
| C. | the letters were chosen in honour of jack kilby, the inventory of the integrated circuit |
| D. | all of the other letters of the alphabet are already in use |
| Answer» D. all of the other letters of the alphabet are already in use | |
| 206. |
A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting |
| A. | two and gates |
| B. | two nand gates |
| C. | two not gates |
| D. | two or gates |
| Answer» B. two nand gates | |
| 207. |
The characteristic of J-K flip-flop is similar to |
| A. | s-r flip-flop |
| B. | d flip-flop |
| C. | t flip-flop |
| D. | gated t flip-flop |
| Answer» B. d flip-flop | |
| 208. |
The S-R, J-K and D inputs are called |
| A. | asynchronous inputs |
| B. | synchronous inputs |
| C. | bidirectional inputs |
| D. | unidirectional inputs |
| Answer» C. bidirectional inputs | |
| 209. |
The term synchronous means _ |
| A. | the output changes state only when any of the input is triggered |
| B. | the output changes state only when the clock input is triggered |
| C. | the output changes state only when the input is reversed |
| D. | the output changes state only when the input follows it |
| Answer» C. the output changes state only when the input is reversed | |
| 210. |
Which of the following is the Universal Flip-flop? |
| A. | s-r flip-flop |
| B. | j-k flip-flop |
| C. | master slave flip-flop |
| D. | d flip-flop |
| Answer» C. master slave flip-flop | |
| 211. |
Which of the following flip-flops is free from the race around the problem? |
| A. | t flip-flop |
| B. | sr flip-flop |
| C. | master-slave flip-flop |
| D. | d flip-flop |
| Answer» B. sr flip-flop | |
| 212. |
How many types of triggering takes place in a flip flops? |
| A. | 3 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» B. 2 | |
| 213. |
S-R type flip-flop can be converted into D type flip-flop if S is connected to R through |
| A. | or gate |
| B. | and gate |
| C. | inverter |
| D. | full adder |
| Answer» D. full adder | |
| 214. |
If one wants to design a binary counter, the preferred type of flip-flop is |
| A. | d type |
| B. | s-r type |
| C. | latch |
| D. | j-k type |
| Answer» E. | |
| 215. |
In a positive edge triggered JK flip flop, a low J and low K produces? |
| A. | high state |
| B. | low state |
| C. | toggle state |
| D. | no change state |
| Answer» E. | |
| 216. |
Master slave flip flop is also referred to as? |
| A. | level triggered flip flop |
| B. | pulse triggered flip flop |
| C. | edge triggered flip flop |
| D. | edge-level triggered flip flop |
| Answer» C. edge triggered flip flop | |
| 217. |
At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as? |
| A. | conversion condition |
| B. | race around condition |
| C. | lock out state |
| D. | forbidden state |
| Answer» C. lock out state | |
| 218. |
D flip-flop is a circuit having |
| A. | 2 nand gates |
| B. | 3 nand gates |
| C. | 4 nand gates |
| D. | 5 nand gates |
| Answer» D. 5 nand gates | |
| 219. |
Input clock of RS flip-flop is given to |
| A. | input |
| B. | pulser |
| C. | output |
| D. | master slave flip-flop |
| Answer» C. output | |
| 220. |
The asynchronous input can be used to set the flip-flop to the |
| A. | 1 state |
| B. | 0 state |
| C. | either 1 or 0 state |
| D. | forbidden state |
| Answer» D. forbidden state | |
| 221. |
The characteristic equation of D-flip-flop implies that |
| A. | the next state is dependent on previous state |
| B. | the next state is dependent on present state |
| C. | the next state is independent of previous state |
| D. | the next state is independent of present state |
| Answer» E. | |
| 222. |
Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’? |
| A. | due to its capability to receive data from flip-flop |
| B. | due to its capability to store data in flip-flop |
| C. | due to its capability to transfer the data into flip-flop |
| D. | due to erasing the data from the flip-flop |
| Answer» D. due to erasing the data from the flip-flop | |
| 223. |
Which of the following describes the operation of a positive edge-triggered D flip-flop? |
| A. | if both inputs are high, the output will toggle |
| B. | the output will follow the input on the leading edge of the clock |
| C. | when both inputs are low, an invalid state exists |
| D. | the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock |
| Answer» C. when both inputs are low, an invalid state exists | |
| 224. |
Which of the following is correct for a D latch? |
| A. | the output toggles if one of the inputs is held high |
| B. | q output follows the input d when the enable is high |
| C. | only one of the inputs can be high at a time |
| D. | the output complement follows the input when enabled |
| Answer» C. only one of the inputs can be high at a time | |
| 225. |
A positive edge-triggered D flip-flop will store a 1 when |
| A. | the d input is high and the clock transitions from high to low |
| B. | the d input is high and the clock transitions from low to high |
| C. | the d input is high and the clock is low |
| D. | the d input is high and the clock is high |
| Answer» C. the d input is high and the clock is low | |
| 226. |
With regard to a D latch |
| A. | the q output follows the d input when en is low |
| B. | the q output is opposite the d input when en is low |
| C. | the q output follows the d input when en is high |
| D. | the q output is high regardless of en’s input state |
| Answer» D. the q output is high regardless of en’s input state | |
| 227. |
Which of the following is correct for a gated D flip-flop? |
| A. | the output toggles if one of the inputs is held high |
| B. | only one of the inputs can be high at a time |
| C. | the output complement follows the input when enabled |
| D. | q output follows the input d when the enable is high |
| Answer» E. | |
| 228. |
In D flip-flop, if clock input is HIGH & D=1, then output is |
| A. | 0 |
| B. | 1 |
| C. | forbidden |
| D. | toggle |
| Answer» B. 1 | |
| 229. |
A D flip-flop can be constructed from an _ flip-flop. |
| A. | s-r |
| B. | j-k |
| C. | t |
| D. | s-k |
| Answer» B. j-k | |
| 230. |
The D flip-flop has output/outputs. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 1 |
| Answer» B. 3 | |
| 231. |
The D flip-flop has input. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 232. |
MOS is being used in |
| A. | lsi |
| B. | vlsi |
| C. | msi |
| D. | both lsi and vlsi |
| Answer» E. | |
| 233. |
Critical defects per unit chip area is for a MOS transistor. |
| A. | high |
| B. | low |
| C. | neutral |
| D. | very high |
| Answer» C. neutral | |
| 234. |
Why MOSFET is preferred over BJT in IC components? |
| A. | mosfet has low packing density |
| B. | mosfet has medium packing density |
| C. | mosfet has high packing density |
| D. | mosfet has no packing density |
| Answer» B. mosfet has medium packing density | |
| 235. |
What is used to higher the speed of operation in MOSFET fabrication? |
| A. | ceramic gate |
| B. | silicon dioxide |
| C. | silicon nitride |
| D. | poly silicon gate |
| Answer» E. | |
| 236. |
A technique used to reduce the magnitude of threshold voltage of MOSFET is the |
| A. | use of complementary mosfet |
| B. | use of silicon nitride |
| C. | using thin film technology |
| D. | increasing potential of the channel |
| Answer» C. using thin film technology | |
| 237. |
Which insulating layer used in the fabrication of MOSFET? |
| A. | aluminium oxide |
| B. | silicon nitride |
| C. | silicon dioxide |
| D. | aluminium nitrate |
| Answer» D. aluminium nitrate | |
| 238. |
What are the types of MOSFET devices available? |
| A. | p-type enhancement type mosfet |
| B. | n-type enhancement type mosfet |
| C. | depletion type mosfet |
| D. | all of the mentioned |
| Answer» E. | |
| 239. |
The full form of MOS is |
| A. | metal oxide semiconductor |
| B. | metal oxygen semiconductor |
| C. | metallic oxide semiconductor |
| D. | metallic oxygen semiconductor |
| Answer» B. metal oxygen semiconductor | |
| 240. |
When both inputs of SR latches are high, the latch goes |
| A. | unstable |
| B. | stable |
| C. | metastable |
| D. | bistable |
| Answer» D. bistable | |
| 241. |
When both inputs of SR latches are low, the latch |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | it remains in its previously set or reset state |
| D. | it goes to its next set or reset state |
| Answer» D. it goes to its next set or reset state | |
| 242. |
When a high is applied to the Set line of an SR latch, then |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | q output goes low |
| D. | both q and q’ go high |
| Answer» B. q’ output goes high | |
| 243. |
The inputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | j and k |
| Answer» D. j and k | |
| 244. |
The first step of analysis procedure of SR latch is to |
| A. | label inputs |
| B. | label outputs |
| C. | label states |
| D. | label tables |
| Answer» C. label states | |
| 245. |
The SR latch consists of |
| A. | 1 input |
| B. | 2 inputs |
| C. | 3 inputs |
| D. | 4 inputs |
| Answer» C. 3 inputs | |
| 246. |
The outputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | q and q’ |
| Answer» E. | |
| 247. |
The full form of SR is |
| A. | system rated |
| B. | set reset |
| C. | set ready |
| D. | set rated |
| Answer» C. set ready | |
| 248. |
How many types of latches are __ |
| A. | 4 |
| B. | 3 |
| C. | 2 |
| D. | 5 |
| Answer» B. 3 | |
| 249. |
Two stable states of latches are |
| A. | astable & monostable |
| B. | low input & high output |
| C. | high output & low output |
| D. | low output & high input |
| Answer» D. low output & high input | |
| 250. |
Why latches are called a memory devices? |
| A. | it has capability to stare 8 bits of data |
| B. | it has internal memory of 4 bit |
| C. | it can store one bit of data |
| D. | it can store infinite amount of data |
| Answer» D. it can store infinite amount of data | |