MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 165 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 101. |
Directions: It consists of two statements, one labelled as the ‘Statement (I)’ and the other as ‘Statement (II). Examine these two statements carefully and select the answer using the codes given below:Statement (I): As applied to flip flops, asynchronous inputs are overriding inputs.Statement (II): Direct inputs of flips flops are effective even in the absence of the control/clock input. |
| A. | Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I) |
| B. | Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I) |
| C. | Statement (I) is true but Statement (II) is false |
| D. | Statement (I) is false but Statement (II) is true |
| Answer» B. Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I) | |
| 102. |
A modulus-12 ring counter requires a minimum of |
| A. | 10 flip-flops |
| B. | 12 flip-flop |
| C. | 8 flip-flop |
| D. | 6 flip-flop |
| Answer» C. 8 flip-flop | |
| 103. |
In SISO shift register, the time delay Δt is given by:WhereN is the number of stagesfc is the clock frequency |
| A. | N2 fc |
| B. | N2/fc |
| C. | Nfc |
| D. | N/fc |
| Answer» E. | |
| 104. |
In a J-K flip flop, when Jn = 0 and Kn = 1, the output Qn + 1 will have a value of: |
| A. | 1 |
| B. | 0 |
| C. | Qn |
| D. | \(\overline {{Q_n}}\) |
| Answer» C. Qn | |
| 105. |
Assertion (A): In a parallel - in - serial out shift register, data is loaded one bit at a time.Reason (R): A serial-in-serial-out shift register can be used to introduce a time delay in the circuits. |
| A. | Both (A) and (R) are true and (R) is the correct explanation of (A) |
| B. | Both (A) and (R) are true, but (R) is not the correct explanation of (A) |
| C. | (A) is true, but (R) is false |
| D. | (A) is false, but (R) is true |
| Answer» E. | |
| 106. |
For the circuit given below with the initial condition Y2Y1Y0 = 001, what is the output after three clock cycles? |
| A. | 100 |
| B. | 101 |
| C. | 110 |
| D. | 111 |
| Answer» C. 110 | |
| 107. |
In case of R-S flip-flop for R = 0 and S = 1, the action of flip-flop is: |
| A. | Set |
| B. | Reset |
| C. | No change |
| D. | Forbidden |
| Answer» B. Reset | |
| 108. |
A sequential circuit using D flip-flop and logic gates is shown in the figure, where X and Y are inputs and Z is the output. The circuit is |
| A. | S – R flip-flop with X = S and Y = R |
| B. | S – R flip-flop with X = R and Y = S |
| C. | J – K flip-flop with X = J and Y = K |
| D. | J – K flip-flop with X = K and Y = J |
| Answer» E. | |
| 109. |
For SR flip-flop with NOR gates, the undefined state is |
| A. | S = 0, R = 0 |
| B. | S = 0, R = 1 |
| C. | S = 1, R = 1 |
| D. | S = 1, R = 0 |
| Answer» D. S = 1, R = 0 | |
| 110. |
A cascade of three identical modulo-5 counters has an overall modulus of |
| A. | 5 |
| B. | 25 |
| C. | 125 |
| D. | 625 |
| Answer» D. 625 | |
| 111. |
Maximum count value of a n bit counter is |
| A. | 2n -1 |
| B. | 2n |
| C. | 22n |
| D. | 2n + 1 |
| Answer» B. 2n | |
| 112. |
A negative edge triggered flip flop transfers data from input to output on the: |
| A. | WITHOUT transition of clock pulse |
| B. | LOW to HIGH transition of clock pulse |
| C. | HIGH to LOW transition of clock pulse |
| D. | BEFORE transition of clock pulse |
| Answer» D. BEFORE transition of clock pulse | |
| 113. |
An SR flip-flop does not accept the input entry when |
| A. | both inputs zero |
| B. | zero at R and one at S |
| C. | zero at S and one at R |
| D. | both inputs at one |
| Answer» E. | |
| 114. |
A 4-bit synchronous counter has flip-flops having propagation delay of 50 ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be |
| A. | 20 MHz |
| B. | 50 MHz |
| C. | 14.3 MHz |
| D. | 5 MHz |
| Answer» D. 5 MHz | |
| 115. |
In a master-slave JK flip-flop |
| A. | both master and slave are positive- edge-triggered |
| B. | both master and slave are negative- edge-triggered |
| C. | master is positive-edge-triggered and slave is negative-edge- triggered |
| D. | master is negative-edge-triggered and slave is positive-edge-triggered |
| Answer» D. master is negative-edge-triggered and slave is positive-edge-triggered | |
| 116. |
How many flipflops are required to build binary counter to count from 0 to 1023? |
| A. | 8 |
| B. | 10 |
| C. | 4 |
| D. | 23 |
| Answer» C. 4 | |
| 117. |
A flip-flop whose state changes on the rising or falling edge of a clock pulse is called: |
| A. | leading edge flip-flop |
| B. | level-triggered flip-flop |
| C. | edge-triggered flip-flop |
| D. | rising edge flip-flop |
| Answer» D. rising edge flip-flop | |
| 118. |
Minimum number of flip flops required for Modulus 15 counter is |
| A. | 15 |
| B. | 16 |
| C. | 4 |
| D. | 3 |
| Answer» D. 3 | |
| 119. |
Asynchronous circuits are usually faster than synchronous circuits because |
| A. | the frequency of the clock used is very high |
| B. | they are free running and do not depend on the frequency of the clock |
| C. | the orderly execution of operations in these circuits is controlled by clock pulse |
| D. | the completion and initiation signals are not needed |
| Answer» C. the orderly execution of operations in these circuits is controlled by clock pulse | |
| 120. |
A circuit consists of two clocked JK flip-flops connected as follows: \({J_0} = {K_0} = {\overline Q _1}\), \({J_1} = {Q_0}\) and \({K_1} = {\overline Q _1}\).Each flip-flop receives the clock input simultaneously. The circuit acts as a |
| A. | Counter of mod 3 |
| B. | Counter of mod 4 |
| C. | shift-left register |
| D. | Shift-right register |
| Answer» B. Counter of mod 4 | |
| 121. |
A 4-bit ripple counter consisting of flip-flps that each have a propagation delay of 12ns from clock to Q output. For the counter to recycle from 1111 to 0000, it takes a total of: |
| A. | 12ns |
| B. | 24ns |
| C. | 48ns |
| D. | 26ns |
| Answer» D. 26ns | |
| 122. |
An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing |
| A. | NOR gates to NAND gates |
| B. | inverters to buffers |
| C. | NOR gates to NAND gates and inverters to buffers |
| D. | 5 V to ground |
| Answer» E. | |
| 123. |
______ is commonly used to interface output devices. |
| A. | Buffer |
| B. | Pulse generator |
| C. | Accumulator |
| D. | Latch |
| Answer» E. | |
| 124. |
A 4-bit module 6 ripple counter uses JK flip flop. If the propagation by each flip flop is 50 ns. The maximum clock frequency be used |
| A. | 5 MHz |
| B. | 10 MHz |
| C. | 4 MHz |
| D. | 20 MHz |
| Answer» B. 10 MHz | |
| 125. |
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are QAQB = 00,01,10, and 11.Assume that XIN is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state QAQB = 00 and clocked, after a few clock cycles, it starts cycling through |
| A. | all of the four possible states if XIN = 1 |
| B. | three of the four possible states if XIN = 0 |
| C. | only two of the four possible states if XIN = 1 |
| D. | only two of the four possible states if XIN = 0 |
| Answer» E. | |
| 126. |
A flip-flop is a |
| A. | Combinational logic circuit and edge sensitive |
| B. | Sequential logic circuit and edge sensitive |
| C. | Combinational logic circuit and level sensitive |
| D. | Sequential logic circuit and level sensitive |
| Answer» C. Combinational logic circuit and level sensitive | |
| 127. |
A circuit consists of two synchronously clocked J-K flip-flops connected as follows :J0 = K0 = Q̅1, J1 = Q1, K1 = Q̅ 0. The circuit acts as a |
| A. | Counter of mod 2 |
| B. | Counter of mod 3 |
| C. | Shift-right register |
| D. | Shift-left register |
| Answer» B. Counter of mod 3 | |
| 128. |
A basic memory storage element in a digital system is: |
| A. | Flip flop |
| B. | Counter |
| C. | Multiplexer |
| D. | Encoder |
| Answer» B. Counter | |
| 129. |
A finite state machine in which1. the output is a function of the current state and Inputs2. the output is a function of only the current stateWhich of the following machines is respectively correct for these styles? |
| A. | Mealy machine and Moore machine |
| B. | Moore machine and Mealy machine |
| C. | State machine and Mealy machine |
| D. | State machine and State machine |
| Answer» B. Moore machine and Mealy machine | |
| 130. |
For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.If the clock (Clk) frequency is 1 GHz, then the counter behaves as a |
| A. | mod-5 counter |
| B. | mod-6 counter |
| C. | mod-7 counter |
| D. | mod-8 counter |
| Answer» E. | |
| 131. |
How is a J-K Flip Flop made to toggle |
| A. | J = 0, K = 0 |
| B. | J = 1, K = 0 |
| C. | J = 0, K = 1 |
| D. | J = 1, K = 1 |
| Answer» E. | |
| 132. |
Consider the following sequential circuit.What are values of Q0 and Q1 after 4 clock cycles, if the initial values are 00? |
| A. | 11 |
| B. | 01 |
| C. | 10 |
| D. | 00 |
| Answer» E. | |
| 133. |
If J = K in case of J – K flip-flop, then the resulting flip-flop is known as: |
| A. | T FLIP-FLOP |
| B. | D FLIP-FLOP |
| C. | J-K FLIP FLOP |
| D. | S-R FLIP-FLOP |
| Answer» B. D FLIP-FLOP | |
| 134. |
A finite state machine |
| A. | is same as that of an abstract model of a sequential circuit |
| B. | consists of combinational logic circuits only |
| C. | contains an infinite number of memory devices |
| D. | does not exist in practice |
| Answer» B. consists of combinational logic circuits only | |
| 135. |
How many minimum number of Flip-Flops are required for mod-14 counter? |
| A. | 4 |
| B. | 14 |
| C. | 7 |
| D. | 16 |
| Answer» B. 14 | |
| 136. |
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs |
| A. | Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively |
| B. | Q1 Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively |
| C. | Q1 Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively |
| D. | Q1 Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively |
| Answer» C. Q1 Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively | |
| 137. |
A three-bit shift register is shown below. To have content 000 again, the number of clock pulses required would be: |
| A. | 2 |
| B. | 3 |
| C. | 6 |
| D. | 7 |
| Answer» D. 7 | |
| 138. |
A pulse train with a frequency of 1 MHz is counted using a mod-1024 ripple counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per flip-flop stage is |
| A. | 100 ns |
| B. | 50 ns |
| C. | 20 ns |
| D. | 10 ns |
| Answer» B. 50 ns | |
| 139. |
A decade counter requires |
| A. | 2 Flip flops |
| B. | 3 Flip flops |
| C. | 4 Flip flops |
| D. | 100 Flip flops |
| Answer» D. 100 Flip flops | |
| 140. |
Following pulse is applied to an SR flip flop.If Δt is propagation delay, which of the following relations should hold to avoid the race around condition? |
| A. | tp < Δt < T |
| B. | Δt < tp < T |
| C. | 2Δt < tp |
| D. | 2Δt < tp < T |
| Answer» B. Δt < tp < T | |
| 141. |
Calculate the maximum clock frequency at which a 4-bit asynchronous counter can work reliably. Assume the propagation delay of each flip-flop to be 40 ns and the width of the strobe pulse to be 20 ns. |
| A. | 12.5 MHz |
| B. | 6.25 MHz |
| C. | 5.56 MHz |
| D. | 16.67 MHz |
| Answer» D. 16.67 MHz | |
| 142. |
Ring and johnson counters are _______. |
| A. | asynchronous counters |
| B. | synchronous counters |
| C. | true binary counters |
| D. | asynchronous and true binary counters |
| Answer» C. true binary counters | |
| 143. |
A multiplexed display circuit uses a technique called time division modulation. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 144. |
A _________ shift register can shift stored data either left or right. |
| A. | bidirectional |
| B. | tri-state |
| C. | universal |
| D. | bidirectional universal |
| Answer» E. | |
| 145. |
An asynchronous decade counter increases its value by ten for each clock pulse. |
| A. | 1 |
| B. | |
| Answer» C. | |
| 146. |
When two counters are cascaded, the overall mod number is equal to the __________ of their individual mod numbers. |
| A. | product |
| B. | sum |
| C. | log |
| D. | reciprocal |
| Answer» B. sum | |
| 147. |
The modulus (mod) of a counter is the same as its maximum count (N). |
| A. | 1 |
| B. | |
| Answer» B. | |
| 148. |
A parallel-in, serial-out shift register enters all data bits simultaneously and transfers them out one bit at a time. |
| A. | 1 |
| B. | |
| Answer» B. | |
| 149. |
When the output of a tri-state shift register is disabled, the output level is placed in a: |
| A. | float state |
| B. | LOW state |
| C. | high impedance state |
| D. | float state and a high impedance state |
| Answer» E. | |
| 150. |
What is meant by parallel-loading the register? |
| A. | Shifting the data in all flip-flops simultaneously |
| B. | Loading data in two of the flip-flops |
| C. | Loading data in all four flip-flops at the same time |
| D. | Momentarily disabling the synchronous SET and RESET inputs |
| Answer» D. Momentarily disabling the synchronous SET and RESET inputs | |