Assertion (A): In a parallel - in - serial out shift register, data is loaded one bit at a time.Reason (R): A serial-in-serial-out shift register can be used to introduce a time delay in the circuits.

Both (A) and (R) are true and (R) is the correct explanation of (A)

Both (A) and (R) are true, but (R) is not the correct explanation of (A)

Assertion (A): In a parallel - in - serial out shift register, data is

1.	Assertion (A): In a parallel - in - serial out shift register, data is loaded one bit at a time.Reason (R): A serial-in-serial-out shift register can be used to introduce a time delay in the circuits.
A.	Both (A) and (R) are true and (R) is the correct explanation of (A)
B.	Both (A) and (R) are true, but (R) is not the correct explanation of (A)
C.	(A) is true, but (R) is false
D.	(A) is false, but (R) is true
Answer» E.

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Assertion (A): In a parallel - in - serial out shift register, data is loaded one bit at a time.Reason (R): A serial-in-serial-out shift register can be used to introduce a time delay in the circuits.

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