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This section includes 9294 Mcqs, each offering curated multiple-choice questions to sharpen your Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 4601. |
In the given figure RC = RL = 1 k , then V0 = |
| A. | 5 V |
| B. | 2.5 V |
| C. | 1 V |
| D. | 0 V |
| Answer» C. 1 V | |
| 4602. |
A 14 pin NOT gate 1C has __________ NOT gates. |
| A. | 8 |
| B. | 6 |
| C. | 5 |
| D. | 4 |
| Answer» C. 5 | |
| 4603. |
F's complement of (2BFD)hex is |
| A. | E 304 |
| B. | D 403 |
| C. | D 402 |
| D. | C 403 |
| Answer» D. C 403 | |
| 4604. |
Which of the following characteristic are necessary for a sequential circuit? It must have 6 gatesIt must have feedbackIts output should depend on past value Which of the above statements are correct? |
| A. | 1, 2, 3 |
| B. | 1, 2 |
| C. | 2, 3 |
| D. | 1, 3 |
| Answer» D. 1, 3 | |
| 4605. |
A digital system is required to amplify a binary encoded audio signal. The user should be able to control the gain of the amplifier from a minimum to a maximum in 100 increments. The minimum number of bits required to encode, in straight binary is, |
| A. | 8 |
| B. | 6 |
| C. | 5 |
| D. | 7 |
| Answer» E. | |
| 4606. |
A 4 bit transistor register has output voltage of high-low-high-low. The binary number stored and its decimal equivalent are |
| A. | 0101 and 5 |
| B. | 0101 and 10 |
| C. | 1010 and 5 |
| D. | 1010 and 10 |
| Answer» E. | |
| 4607. |
Assertion (A): A demultiplexer cannot be used as a decoder Reason (R): A multiplexer selects one of many outputs whereas a decoder selects on output corresponding to coded input. |
| A. | Both A and R are correct and R is correct explanation of A |
| B. | Both A and R are correct but R is not correct explanation of A |
| C. | A is true, R is false |
| D. | A is false, R is true |
| Answer» E. | |
| 4608. |
Hexadecimal number F is called to octal number |
| A. | 15 |
| B. | 16 |
| C. | 17 |
| D. | 18 |
| Answer» D. 18 | |
| 4609. |
A half adder can be used only for adding |
| A. | 1 s |
| B. | 2 s |
| C. | 4 s |
| D. | 8 s |
| Answer» B. 2 s | |
| 4610. |
What is the normal range of analog input voltage? |
| A. | 0 to 1 V |
| B. | 0 to 5 V |
| C. | 5 to 15 V |
| D. | 15V to 30V |
| Answer» C. 5 to 15 V | |
| 4611. |
The inputs to a NAND gate are as shown in the given figure. The waveform of output is |
| A. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/31-419-1.png"> |
| B. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/31-419-2.png"> |
| C. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/31-419-3.png"> |
| D. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/31-419-4.png"> |
| Answer» B. <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/31-419-2.png"> | |
| 4612. |
What do the contents of instruction register specify? |
| A. | Operand for the instruction being executed |
| B. | Op code for the instruction being executed |
| C. | Op code for the instruction to be executed next |
| D. | Operand for the instruction to be executed next |
| Answer» C. Op code for the instruction to be executed next | |
| 4613. |
In the decimal number 27, the digital 2 represents |
| A. | 2 |
| B. | 20 |
| C. | 0.2 |
| D. | 200 |
| Answer» C. 0.2 | |
| 4614. |
In a 4 input AND gate, the total number of High outputs for 16 input states are |
| A. | 16 |
| B. | 8 |
| C. | 4 |
| D. | 1 |
| Answer» E. | |
| 4615. |
Symmetrical square wave of time period 100 s can be obtained from square wave of time period 10 s by using |
| A. | divide by 5 circuit |
| B. | divide by 2 circuit |
| C. | divide by 5 circuit followed by divide by 2 circuit |
| D. | BCD counter |
| Answer» D. BCD counter | |
| 4616. |
The initial state of a Mod-16 counter is 0110. After 37 clock pulses the state of counter will be |
| A. | 1011 |
| B. | 0110 |
| C. | 010 |
| D. | 0001 |
| Answer» B. 0110 | |
| 4617. |
In following figure, the initial contents of the 4-bit serial in parallel out, right shift, shift register as shown in figure are 0110. After 3 clock pulses the contents of the shift register will be |
| A. | 0000 |
| B. | 0101 |
| C. | 1010 |
| D. | 1110 |
| Answer» D. 1110 | |
| 4618. |
For the logic circuit of the given figure, the minimized expression is |
| A. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/30-396.png"> |
| B. | Y = A + B + C |
| C. | Y = A + B |
| D. | Y = ABC |
| Answer» B. Y = A + B + C | |
| 4619. |
Binary multiplication can be done by repeated addition. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 4620. |
Assertion (A): In totem pole output the output impedance is low.Reason (R): TTL gate with active pull up should not be used in wired AND connection. |
| A. | Both A and R are correct and R is correct explanation of A |
| B. | Both A and R are correct but R is not correct explanation of A |
| C. | A is true, R is false |
| D. | A is false, R is true |
| Answer» C. A is true, R is false | |
| 4621. |
A 4 bit synchronous counter uses flip flops with a delay time of 15 ns each. The time required for change of state is |
| A. | 15 ns |
| B. | 30 ns |
| C. | 45 ns |
| D. | 60 ns |
| Answer» B. 30 ns | |
| 4622. |
TTL logic is preferred to DRL logic because |
| A. | greater fan-out is possible |
| B. | greater logic levels are possible |
| C. | greater fan-in is possible |
| D. | less power consumption is achieve |
| Answer» B. greater logic levels are possible | |
| 4623. |
Assertion (A): Schottky transistors are preferred over normal transistors in digital circuits Reason (R): A Schottky transistor when used as a switch, between cutoff and active region. |
| A. | Both A and R are correct and R is correct explanation of A |
| B. | Both A and R are correct but R is not correct explanation of A |
| C. | A is true, R is false |
| D. | A is false, R is true |
| Answer» B. Both A and R are correct but R is not correct explanation of A | |
| 4624. |
The inputs A and B of the given figure are applied to a two input NOR gate. The output waveform is |
| A. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/23-275-1.png"> |
| B. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/23-275-2.png"> |
| C. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/23-275-3.png"> |
| D. | <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/23-275-4.png"> |
| Answer» C. <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/23-275-3.png"> | |
| 4625. |
In the circuit of the given figure, V0 = |
| A. | 5 V |
| B. | 3.1 V |
| C. | 2.5 V |
| D. | 0 |
| Answer» B. 3.1 V | |
| 4626. |
A parallel in-parallel out shift register can be used to introduce delay in digital circuits. |
| A. | True |
| B. | False |
| Answer» C. | |
| 4627. |
A 14 pin AND gate IC has __________ AND gates. |
| A. | 8 |
| B. | 6 |
| C. | 4 |
| D. | 2 |
| Answer» D. 2 | |
| 4628. |
In 8085 microprocessor, how many lines are there in data bus? |
| A. | 6 |
| B. | 8 |
| C. | 2 |
| D. | 16 |
| Answer» C. 2 | |
| 4629. |
The basic shift register operations are |
| A. | serial in - serial out |
| B. | serial in - parallel out |
| C. | parallel in - serial out |
| D. | all of the above |
| Answer» E. | |
| 4630. |
The hexadecimal number 'A0' has the decimal value |
| A. | 80 |
| B. | 256 |
| C. | 100 |
| D. | 160 |
| Answer» E. | |
| 4631. |
A 4 bit ripple counter is in 0000 state. The clock pulses are applied and then removed. The counter reads 0011. The number of clock pulses which have occurred are |
| A. | 3 |
| B. | 3 or 19 |
| C. | 3 or 19 or 35 |
| D. | none of the above |
| Answer» D. none of the above | |
| 4632. |
Assertion (A): The propagation delay in ECL is minimum Reason (R): Transistors used in ECL switch between active and cutoff regions. |
| A. | Both A and R are correct and R is correct explanation of A |
| B. | Both A and R are correct but R is not correct explanation of A |
| C. | A is true, R is false |
| D. | A is false, R is true |
| Answer» B. Both A and R are correct but R is not correct explanation of A | |
| 4633. |
For the design of a sequential circuit having 9 states, minimum number of memory elements required is |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 9 |
| Answer» C. 5 | |
| 4634. |
ICs are |
| A. | analog |
| B. | digital |
| C. | both analog and digital |
| D. | mostly analog |
| Answer» D. mostly analog | |
| 4635. |
In a 5 x 7 dot matrix, format, to store 64 alphanumeric characters we require |
| A. | 1120 bits |
| B. | 2240 bits |
| C. | 33 bits |
| D. | 64 bits |
| Answer» C. 33 bits | |
| 4636. |
In the 8421 BCD code, the decimal number 125, is written as |
| A. | 1111101 |
| B. | 0001 0010 0101 |
| C. | 7 D |
| D. | none of these |
| Answer» B. 0001 0010 0101 | |
| 4637. |
110.112 x 1102 = __________ 10 |
| A. | 40.5 |
| B. | 30.5 |
| C. | 20.5 |
| D. | 10.5 |
| Answer» B. 30.5 | |
| 4638. |
Assertion (A): Different symbols are used for different gatesReason (R): IEEE symbols are the same as traditional symbols for gates. |
| A. | Both A and R are correct and R is correct explanation of A |
| B. | Both A and R are correct but R is not correct explanation of A |
| C. | A is true, R is false |
| D. | A is false, R is true |
| Answer» D. A is false, R is true | |
| 4639. |
10112 x 1012 = __________ 10 |
| A. | 55 |
| B. | 45 |
| C. | 35 |
| D. | 25 |
| Answer» B. 45 | |
| 4640. |
Am equivalent 2's complement representation of the 2's complement number 1101 is |
| A. | 110100 |
| B. | 001101 |
| C. | 110111 |
| D. | 111101 |
| Answer» E. | |
| 4641. |
In a 7 segment display the segments a, c, d, f, g are lit. The decimal number displayed will be |
| A. | 9 |
| B. | 5 |
| C. | 4 |
| D. | 2 |
| Answer» C. 4 | |
| 4642. |
A combination circuit is one in which the output depends on |
| A. | input combination at that time |
| B. | input combination and previous output |
| C. | input combination and previous input |
| D. | present output and previous output |
| Answer» B. input combination and previous output | |
| 4643. |
For the logic circuit of the given figure the simplified Boolean equation |
| A. | Y = (A + B) (C + D) (E + F) |
| B. | Y = A = B + C + D + E + F |
| C. | ABCDEF |
| D. | ABC + DEF |
| Answer» B. Y = A = B + C + D + E + F | |
| 4644. |
The minimum number of comparators required to build an 8 bit flash ADC is |
| A. | 8 |
| B. | 63 |
| C. | 255 |
| D. | 256 |
| Answer» D. 256 | |
| 4645. |
For a Mod-64 synchronous counter the number of flip flops and AND gates needed is |
| A. | 6 and 4 respectively |
| B. | 4 and 6 respectively |
| C. | 7 and 5 respectively |
| D. | 5 and 7 respectively |
| Answer» B. 4 and 6 respectively | |
| 4646. |
A 4 bit DAC gives an output of 4.5 V for input of 1001. If input is 0110, the output is |
| A. | 1.5 V |
| B. | 2.0 V |
| C. | 3.0 V |
| D. | 4.5 V |
| Answer» D. 4.5 V | |
| 4647. |
Out of 5 M x 8, 1 M x 16, 2 M x 16 and 3M x 8 memories, which memory can store more bits? |
| A. | 5 M x 8 |
| B. | 2 M x 16 |
| C. | 3 M x 8 |
| D. | 1 M x 16 |
| Answer» B. 2 M x 16 | |
| 4648. |
What will be FSV in 2 bit BCD D/A converter is a weighted resistor type with ER = 1V, R = 1 M and Rf = 10K |
| A. | 0.99 V |
| B. | 0.9 V |
| C. | 0.1 V |
| D. | 0 |
| Answer» B. 0.9 V | |
| 4649. |
In a 4 bit ripple counter using flip flops with tpd = 40 ns, the maximum frequency can be |
| A. | 1.25 MHz |
| B. | 3.25 MHz |
| C. | 6.25 MHz |
| D. | 12.5 MHz |
| Answer» D. 12.5 MHz | |
| 4650. |
In a JK Master slave flip flop |
| A. | both master and slave are positively clocked |
| B. | both master and slave are negatively clocked |
| C. | master is positively clocked and slave is negatively clocked |
| D. | master is negatively clocked and slave is positively clocked |
| Answer» D. master is negatively clocked and slave is positively clocked | |