2291 + Mcqs in Digital Electronics Page 27 McqOptions

1301.	Multivibrators must be level-triggered.
A.	True
B.	False
Answer» C.

Discussion

1302.	Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.
A.	True
B.	False
Answer» C.

Discussion

1303.	A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.
A.	True
B.	False
Answer» B. False

Discussion

1304.	When the output of the NOR gate S-R flip-flop is and , the inputs are .
A.	True
B.	False
Answer» C.

Discussion

1305.	Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.
A.	True
B.	False
Answer» C.

Discussion

1306.	The frequency of the clock waveform is defined as the reciprocal of the clock period.
A.	True
B.	False
Answer» B. False

Discussion

1307.	A one-shot circuit is also known as a timer.
A.	True
B.	False
Answer» C.

Discussion

1308.	An electromechanical relay is operated manually.
A.	True
B.	False
Answer» C.

Discussion

1309.	The S-R flip-flop has no invalid or unused state.
A.	True
B.	False
Answer» C.

Discussion

1310.	The ability to manufacture smaller, more dense components has been fulfilled by SMD.
A.	True
B.	False
Answer» B. False

Discussion

1311.	Serial communications cannot be sped up.
A.	True
B.	False
Answer» C.

Discussion

1312.	Manual switches and relays have identical ON and OFF resistances.
A.	True
B.	False
Answer» C.

Discussion

1313.	Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.
A.	True
B.	False
Answer» C.

Discussion

1314.	It takes four flip-flops to act as a divide-by-4 frequency divider.
A.	True
B.	False
Answer» C.

Discussion

1315.	The gated S-R flip-flop is asynchronous.
A.	True
B.	False
Answer» C.

Discussion

1316.	A flip-flop is in the CLEAR condition when .
A.	True
B.	False
Answer» C.

Discussion

1317.	A D latch has one data-input line.
A.	True
B.	False
Answer» B. False

Discussion

1318.	The 7474 has two distinct types of inputs: synchronous and asynchronous.
A.	True
B.	False
Answer» B. False

Discussion

1319.	Most basic latches and flip-flops are available in IC packages of eight latches or flip-flops with a common clock.
A.	True
B.	False
Answer» B. False

Discussion

1320.	Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.
A.	True
B.	False
Answer» B. False

Discussion

1321.	The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.
A.	True
B.	False
Answer» B. False

Discussion

1322.	A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.
A.	True
B.	False
Answer» C.

Discussion

1323.	Parallel data transfers between two different sets of registers require more than one shift pulse.
A.	True
B.	False
Answer» C.

Discussion

1324.	A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.
A.	True
B.	False
Answer» C.

Discussion

1325.	When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.
A.	True
B.	False
Answer» C.

Discussion

1326.	All multivibrators require feedback.
A.	True
B.	False
Answer» B. False

Discussion

1327.	The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.
A.	True
B.	False
Answer» B. False

Discussion

1328.	Edge-triggered flip-flops can be identified by the triangle on the clock input.
A.	True
B.	False
Answer» B. False

Discussion

1329.	Using the CPLD design environment, we can simulate any combinations of inputs and observe the resulting output to check for proper circuit operation.
A.	True
B.	False
Answer» B. False

Discussion

1330.	The exclusive-OR provides a LOW input if one input or the other input is HIGH.
A.	True
B.	False
Answer» C.

Discussion

1331.	The odd/even parity system would require a sixth bit to be added to a 4-bit system.
A.	True
B.	False
Answer» C.

Discussion

1332.	Electrical noise does not affect the transmission of binary information.
A.	True
B.	False
Answer» C.

Discussion

1333.	In an exclusive-OR, both inputs cannot be HIGH to provide a HIGH output.
A.	True
B.	False
Answer» B. False

Discussion

1334.	Precise timing is not important in digital signals.
A.	True
B.	False
Answer» C.

Discussion

1335.	A plot of voltage versus time is called a timing diagram.
A.	True
B.	False
Answer» B. False

Discussion

1336.	The CMOS uses bipolar transistors instead of MOSFET.
A.	True
B.	False
Answer» C.

Discussion

1337.	Most modern digital systems are based on semiconductor technology.
A.	True
B.	False
Answer» B. False

Discussion

1338.	The 7475 is an example of an IC D latch (also called a bistable latch) that contains four transparent D latches.
A.	True
B.	False
Answer» B. False

Discussion

1339.	The SO package is available for the most popular TTL and CMOS digital logic and analog IC devices.
A.	True
B.	False
Answer» B. False

Discussion

1340.	The ________ is the time interval immediately following the active transition of the clock signal.
A.	hold time
B.	setup time
C.	over-time
D.	hang-time
Answer» B. setup time

Discussion

1341.	The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.
A.	logic level
B.	flip-flop
C.	edge-detector circuit
D.	toggle detector
Answer» C. edge-detector circuit

Discussion

1342.	When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.
A.	be invalid
B.	not change
C.	remain unchanged
D.	toggle
Answer» E.

Discussion

1343.	What type of multivibrator is a latch?
A.	Astable
B.	Monostable
C.	Bistable
D.	It depends on the type of latch.
Answer» D. It depends on the type of latch.

Discussion

1344.	If an input is activated by a signal transition, it is ________.
A.	hair-triggered
B.	line-triggered
C.	pulse-triggered
D.	edge-triggered
Answer» E.

Discussion

1345.	The action of ________ a FF or latch is also called resetting.
A.	breaking
B.	clearing
C.	freeing
D.	changing
Answer» C. freeing

Discussion

1346.	The advantage of a J-K flip-flop over an S-R FF is that ________.
A.	it has fewer gates
B.	it has only one output
C.	it has no invalid states
D.	it does not require a clock input
Answer» D. it does not require a clock input

Discussion

1347.	Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.
A.	PROCESS
B.	computer
C.	simulator
D.	primitive library
Answer» D. primitive library

Discussion

1348.	The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.
A.	capacitor
B.	inductor
C.	resistor
D.	LED
Answer» B. inductor

Discussion

1349.	The signal used to identify edge-triggered flip-flops is ________.
A.	a bubble on the clock input
B.	an inverted "L" on the output
C.	the letter "E" on the enable input
D.	a triangle on the clock input
Answer» E.

Discussion

1350.	In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.
A.	function
B.	signal
C.	semicolon
D.	colon
Answer» E.

Discussion

Explore topic-wise MCQs in Engineering.

Multivibrators must be level-triggered.

Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.

A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.

When the output of the NOR gate S-R flip-flop is and , the inputs are .

Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.

The frequency of the clock waveform is defined as the reciprocal of the clock period.

A one-shot circuit is also known as a timer.

An electromechanical relay is operated manually.

The S-R flip-flop has no invalid or unused state.

The ability to manufacture smaller, more dense components has been fulfilled by SMD.

Serial communications cannot be sped up.

Manual switches and relays have identical ON and OFF resistances.

Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.

It takes four flip-flops to act as a divide-by-4 frequency divider.

The gated S-R flip-flop is asynchronous.

A flip-flop is in the CLEAR condition when .

A D latch has one data-input line.

The 7474 has two distinct types of inputs: synchronous and asynchronous.

Most basic latches and flip-flops are available in IC packages of eight latches or flip-flops with a common clock.

Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.

The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.

A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

Parallel data transfers between two different sets of registers require more than one shift pulse.

A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.

When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.

All multivibrators require feedback.

The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

Edge-triggered flip-flops can be identified by the triangle on the clock input.

Using the CPLD design environment, we can simulate any combinations of inputs and observe the resulting output to check for proper circuit operation.

The exclusive-OR provides a LOW input if one input or the other input is HIGH.

The odd/even parity system would require a sixth bit to be added to a 4-bit system.

Electrical noise does not affect the transmission of binary information.

In an exclusive-OR, both inputs cannot be HIGH to provide a HIGH output.

Precise timing is not important in digital signals.

A plot of voltage versus time is called a timing diagram.

The CMOS uses bipolar transistors instead of MOSFET.

Most modern digital systems are based on semiconductor technology.

The 7475 is an example of an IC D latch (also called a bistable latch) that contains four transparent D latches.

The SO package is available for the most popular TTL and CMOS digital logic and analog IC devices.

The ________ is the time interval immediately following the active transition of the clock signal.

The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.

What type of multivibrator is a latch?

If an input is activated by a signal transition, it is ________.

The action of ________ a FF or latch is also called resetting.

The advantage of a J-K flip-flop over an S-R FF is that ________.

Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.

The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.

The signal used to identify edge-triggered flip-flops is ________.

In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.