2291 + Mcqs in Digital Electronics Page 29 McqOptions

1401.	The 555 timer can be used in either the astable or monostable modes.
A.	True
B.	False
Answer» B. False

Discussion

1402.	ICs can perform sequential operations, including counting and data shifting.
A.	True
B.	False
Answer» B. False

Discussion

1403.	An input which can only be accepted when an enable or trigger is present is called asynchronous.
A.	True
B.	False
Answer» C.

Discussion

1404.	A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.
A.	True
B.	False
Answer» C.

Discussion

1405.	Latches are tristate devices whose state normally depends on asynchronous inputs.
A.	True
B.	False
Answer» C.

Discussion

1406.	A logic gate has one or more output terminals and one input terminal.
A.	True
B.	False
Answer» C.

Discussion

1407.	An exclusive-OR gate output is HIGH when the inputs are unequal.
A.	True
B.	False
Answer» B. False

Discussion

1408.	The key to edge-triggered sequential circuits in VHDL is the ________.
A.	ARCHITECTURE
B.	PROCESS
C.	FUNCTION
D.	VARIABLE
Answer» C. FUNCTION

Discussion

1409.	Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.
A.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010a.gif">
B.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010b.gif">
C.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010c.gif">
D.	<img src="/_files/images/digital-electronics/digital-fundamentals/cua7_0010d.gif">
Answer» E.

Discussion

1410.	VHDL does require a special designation for an output with a feedback.
A.	True
B.	False
Answer» B. False

Discussion

1411.	A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.
A.	True
B.	False
Answer» C.

Discussion

1412.	A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.
A.	True
B.	False
Answer» B. False

Discussion

1413.	The term CLEAR always means that .
A.	True
B.	False
Answer» B. False

Discussion

1414.	PRESET and CLEAR inputs are normally synchronous.
A.	True
B.	False
Answer» C.

Discussion

1415.	The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.
A.	<i>PRE, CLR, LOW</i>
B.	<i>ON, OFF, HIGH</i>
C.	<i>START, STOP, LOW</i>
D.	<i>SET, RESET, HIGH</i>
Answer» B. <i>ON, OFF, HIGH</i>

Discussion

1416.	If both inputs of a 2-input NOR gate are connected, the gate will function as an ________.
A.	OR gate
B.	AND gate
C.	inverter
D.	any of the above
Answer» D. any of the above

Discussion

1417.	Assume that you have a 3-input NAND gate but need only a 2-input gate. The unused input should be ________.
A.	connected to ground
B.	left open
C.	connected to a HIGH
D.	any of the above
Answer» D. any of the above

Discussion

1418.	Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.
A.	set
B.	reset
C.	latch
D.	toggle
Answer» E.

Discussion

1419.	In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.
A.	traffic
B.	D
C.	flip-flop
D.	clock
Answer» E.

Discussion

1420.	In a Boolean equation the use of the + symbol represents the OR function.
A.	True
B.	False
Answer» B. False

Discussion

1421.	A node is defined as ________.
A.	a common point in a circuit
B.	a circuit implemented as a sum-of-products
C.	the output signals from a circuit
D.	a shorted input
Answer» B. a circuit implemented as a sum-of-products

Discussion

1422.	Using the universal property of a NAND gate, one or more NAND gates can be used to replace an ________.
A.	OR gate
B.	AND gate
C.	inverter
D.	any of the above
Answer» E.

Discussion

1423.	The expression can be directly implemented using only ________.
A.	an XOR gate
B.	an XNOR gate
C.	an AOI circuit
D.	three 2-input NAND gates
Answer» B. an XNOR gate

Discussion

1424.	An exclusive-NOR gate output is HIGH when the inputs are unequal.
A.	True
B.	False
Answer» C.

Discussion

1425.	An OR gate output is HIGH only if all the inputs are HIGH.
A.	True
B.	False
Answer» C.

Discussion

1426.	A waveform can be enabled or disabled by both AND and OR gates.
A.	True
B.	False
Answer» B. False

Discussion

1427.	An OR array is programmed by blowing fuses to eliminate selected variables from the output functions.
A.	True
B.	False
Answer» B. False

Discussion

1428.	A NAND gate output is LOW only if all the inputs are HIGH.
A.	True
B.	False
Answer» B. False

Discussion

1429.	An AND gate output is LOW if all the inputs are HIGH.
A.	True
B.	False
Answer» C.

Discussion

1430.	Power is connected to pins 7 and 14 of a 7408 quad two-input AND gate IC to allow voltage for all four AND gates on the IC.
A.	True
B.	False
Answer» C.

Discussion

1431.	What is a disadvantage of CMOS in place of TTL?
A.	It switches slower.
B.	It uses less power.
C.	It is smaller.
D.	cost
Answer» B. It uses less power.

Discussion

1432.	Which of the following gates has the exact inverse output of the OR gate for all possible input combinations?
A.	NOR
B.	NOT
C.	NAND
D.	AND
Answer» B. NOT

Discussion

1433.	A logic pulser is used to determine the level of floating in a circuit.
A.	True
B.	False
Answer» C.

Discussion

1434.	The RST pin requires a HIGH to reset the 8051 microcontroller.
A.	True
B.	False
Answer» B. False

Discussion

1435.	In binary, the decimal number 93 converts to ________ digits.
A.	seven
B.	eight
C.	11
D.	five
Answer» B. eight

Discussion

1436.	How many 2-input NOR gates does it take to produce a 2-input NAND gate?
A.	1
B.	2
C.	3
D.	4
Answer» E.

Discussion

1437.	A digital circuit that converts coded information into a familiar or non-coded form is known as an encoder.
A.	True
B.	False
Answer» C.

Discussion

1438.	In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.
A.	True
B.	False
Answer» C.

Discussion

1439.	The postponed symbol () on the output of a flip-flop identifies it as being ________.
A.	a D flip-flop
B.	a J-K flip-flop
C.	pulse triggered
D.	trailing edge-triggered
Answer» D. trailing edge-triggered

Discussion

1440.	Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________.
A.	3
B.	4
C.	5
D.	6
Answer» D. 6

Discussion

1441.	The symbol shown represents a(n) ________.
A.	AND gate
B.	OR gate
C.	NAND gate
D.	NOR gate
Answer» E.

Discussion

1442.	A gate can drive a number of load gate inputs up to its specified ________.
A.	supply voltage
B.	noise margin
C.	fan-in
D.	fan-out
Answer» E.

Discussion

1443.	A truth table illustrates how the input level of a gate responds to all the possible output level combinations.
A.	True
B.	False
Answer» C.

Discussion

1444.	A NOR gate output is LOW if any of its inputs is LOW.
A.	True
B.	False
Answer» C.

Discussion

1445.	As a rule, CMOS has the lowest power consumption of all IC families.
A.	True
B.	False
Answer» B. False

Discussion

1446.	A popular waveform generator is the Johnson shift counter.
A.	True
B.	False
Answer» B. False

Discussion

1447.	If one input to a 2-input AND gate is HIGH, the output reflects the other input.
A.	True
B.	False
Answer» B. False

Discussion

1448.	Good troubleshooting is done by looking at the input signal and how it interacts with the circuits.
A.	True
B.	False
Answer» C.

Discussion

1449.	The output of a NAND gate is LOW when all inputs are HIGH at the same time.
A.	True
B.	False
Answer» B. False

Discussion

1450.	When the output of an AND-OR circuit is complemented, it results in an AND-OR-Invert circuit.
A.	True
B.	False
Answer» B. False

Discussion

Explore topic-wise MCQs in Engineering.

The 555 timer can be used in either the astable or monostable modes.

ICs can perform sequential operations, including counting and data shifting.

An input which can only be accepted when an enable or trigger is present is called asynchronous.

A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.

Latches are tristate devices whose state normally depends on asynchronous inputs.

A logic gate has one or more output terminals and one input terminal.

An exclusive-OR gate output is HIGH when the inputs are unequal.

The key to edge-triggered sequential circuits in VHDL is the ________.

Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

VHDL does require a special designation for an output with a feedback.

A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.

A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.

The term CLEAR always means that .

PRESET and CLEAR inputs are normally synchronous.

The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.

If both inputs of a 2-input NOR gate are connected, the gate will function as an ________.

Assume that you have a 3-input NAND gate but need only a 2-input gate. The unused input should be ________.

Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.

In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.

In a Boolean equation the use of the + symbol represents the OR function.

A node is defined as ________.

Using the universal property of a NAND gate, one or more NAND gates can be used to replace an ________.

The expression can be directly implemented using only ________.

An exclusive-NOR gate output is HIGH when the inputs are unequal.

An OR gate output is HIGH only if all the inputs are HIGH.

A waveform can be enabled or disabled by both AND and OR gates.

An OR array is programmed by blowing fuses to eliminate selected variables from the output functions.

A NAND gate output is LOW only if all the inputs are HIGH.

An AND gate output is LOW if all the inputs are HIGH.

Power is connected to pins 7 and 14 of a 7408 quad two-input AND gate IC to allow voltage for all four AND gates on the IC.

What is a disadvantage of CMOS in place of TTL?

Which of the following gates has the exact inverse output of the OR gate for all possible input combinations?

A logic pulser is used to determine the level of floating in a circuit.

The RST pin requires a HIGH to reset the 8051 microcontroller.

In binary, the decimal number 93 converts to ________ digits.

How many 2-input NOR gates does it take to produce a 2-input NAND gate?

A digital circuit that converts coded information into a familiar or non-coded form is known as an encoder.

In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.

The postponed symbol () on the output of a flip-flop identifies it as being ________.

Assume you have A, B, C, and D available but not their complements. The minimum number of 2-input NAND gates required to implement the equation is ________.

The symbol shown represents a(n) ________.

A gate can drive a number of load gate inputs up to its specified ________.

A truth table illustrates how the input level of a gate responds to all the possible output level combinations.

A NOR gate output is LOW if any of its inputs is LOW.

As a rule, CMOS has the lowest power consumption of all IC families.

A popular waveform generator is the Johnson shift counter.

If one input to a 2-input AND gate is HIGH, the output reflects the other input.

Good troubleshooting is done by looking at the input signal and how it interacts with the circuits.

The output of a NAND gate is LOW when all inputs are HIGH at the same time.

When the output of an AND-OR circuit is complemented, it results in an AND-OR-Invert circuit.

The asynchronous inputs are normally labeled and , and are normally active- inputs.