MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 18 Mcqs, each offering curated multiple-choice questions to sharpen your Embedded Systems knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
What type of cache is used in the Intel 80486DX? |
| A. | logical |
| B. | physical |
| C. | harvard |
| D. | unified |
| Answer» E. | |
| 2. |
Which cache memory solve the cache coherency problem? |
| A. | physical cache |
| B. | logical cache |
| C. | unified cache |
| D. | harvard cache |
| Answer» B. logical cache | |
| 3. |
What is the disadvantage of the physical address? |
| A. | debugging |
| B. | delay |
| C. | data preservation |
| D. | data cleared |
| Answer» C. data preservation | |
| 4. |
WHAT_IS_THE_DISADVANTAGE_OF_THE_PHYSICAL_ADDRESS??$ |
| A. | debugging |
| B. | delay |
| C. | data preservation |
| D. | data cleared |
| Answer» C. data preservation | |
| 5. |
What type of cache is used in the Intel 80486DX?$ |
| A. | logical |
| B. | physical |
| C. | harvard |
| D. | unified |
| Answer» E. | |
| 6. |
Which cache memory solve the cache coherency problem?$ |
| A. | physical cache |
| B. | logical cache |
| C. | unified cache |
| D. | harvard cache |
| Answer» B. logical cache | |
| 7. |
Which of the following approach uses more silicon area? |
| A. | unified |
| B. | harvard |
| C. | logical |
| D. | physical |
| Answer» C. logical | |
| 8. |
Which type of cache is used the SPARC architecture? |
| A. | unified |
| B. | harvard |
| C. | logical |
| D. | physical |
| Answer» D. physical | |
| 9. |
Which of the following has a separate cache for the data and instructions? |
| A. | unified |
| B. | harvard |
| C. | logical |
| D. | physical |
| Answer» C. logical | |
| 10. |
In which of the following the data is preserved within the cache? |
| A. | logical cache |
| B. | physical cache |
| C. | unified cache |
| D. | harvard cache |
| Answer» C. unified cache | |
| 11. |
Which address is used for a tag? |
| A. | memory address |
| B. | logical address |
| C. | cache address |
| D. | location address |
| Answer» C. cache address | |
| 12. |
Which cache mapping have a sequential execution? |
| A. | direct mapping |
| B. | fully associative |
| C. | n way set associative |
| D. | burst fill |
| Answer» E. | |
| 13. |
Which of the following cache mapping can prevent bus thrashing? |
| A. | fully associative |
| B. | direct mapping |
| C. | n way set associative |
| D. | 2 way associative |
| Answer» D. 2 way associative | |
| 14. |
Which mechanism splits the external memory storage into memory pages? |
| A. | index mechanism |
| B. | burst mode |
| C. | distributive mode |
| D. | a software mechanism |
| Answer» B. burst mode | |
| 15. |
Which mapping of cache is inefficient in software viewpoint? |
| A. | fully associative |
| B. | 2 way associative |
| C. | 16 way associative |
| D. | direct mapping |
| Answer» E. | |
| 16. |
How many comparators present in the direct mapping cache? |
| A. | 3 |
| B. | 2 |
| C. | 1 |
| D. | 4 |
| Answer» D. 4 | |
| 17. |
What is the disadvantage of a fully associative cache? |
| A. | hardware |
| B. | software |
| C. | memory |
| D. | peripherals |
| Answer» B. software | |
| 18. |
Which of the following cache has a separate comparator for each entry? |
| A. | direct mapped cache |
| B. | fully associative cache |
| C. | 2-way associative cache |
| D. | 16-way associative cache |
| Answer» C. 2-way associative cache | |