MCQOPTIONS
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This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
TO_FILTER_THE_OUTPUT,_A_0.047MICROFARADS,_12V_CAPACITOR_IS_CONNECTED_BETWEEN_THE_PINS?$ |
| A. | CAP and ground |
| B. | Output pin and ground |
| C. | CAP and Vcc |
| D. | NMI and ground |
| Answer» B. Output pin and ground | |
| 2. |
The signal that causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions are$ |
| A. | BUSY (active low) |
| B. | PEACK (active low) |
| C. | PEREQ |
| D. | ERROR (active low) |
| Answer» E. | |
| 3. |
The minimum number of clock cycles required in an input pulse width of the RESET pin i? |
| A. | 4 |
| B. | 2 |
| C. | 8 |
| D. | 16 |
| Answer» E. | |
| 4. |
The pin that is used to insert wait states in a bus cycle is |
| A. | WAIT |
| B. | BHE (active low) |
| C. | READY (active low) |
| D. | WAIT(active low) |
| Answer» D. WAIT(active low) | |
| 5. |
The LOCK (active low) is activated automatically by hardware using |
| A. | XCHG signal |
| B. | Interrupt acknowledge |
| C. | Descriptor table access |
| D. | All of the mentioned |
| Answer» E. | |
| 6. |
If M/IO (active low) signal is ‘0’ then it indicates$ |
| A. | I/O cycle |
| B. | Memory cycle |
| C. | I/O cycle or INTA cycle |
| D. | I/O cycle or HALT cycle |
| Answer» D. I/O cycle or HALT cycle | |
| 7. |
The signals S1 (active low), S2 (active low) are |
| A. | output signals |
| B. | indicate initiation of bus cycle |
| C. | define type of bus cycle with M/IO (active low) |
| D. | all of the mentioned |
| Answer» E. | |
| 8. |
The 8 address lines, A23-A16 of 80286 are zero during |
| A. | memory transfer |
| B. | address transfer |
| C. | memory to processor transfer |
| D. | I/O transfer |
| Answer» E. | |
| 9. |
The clock frequency applied at the CLK pin is internally divided by |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 1 |
| Answer» B. 4 | |
| 10. |
The 80286 is available in the package as |
| A. | 68-pin PLCC (plastic leaded chip carrier) |
| B. | 68-pin LCC (lead less chip carrier) |
| C. | 68-pin PGA (pin grid array) |
| D. | all of the mentioned |
| Answer» E. | |