MCQOPTIONS
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MCQOPTIONS
This section includes 11 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Which of the following command is used to make all the internal registers of 8237 clear? |
| A. | clear first/last flipflop |
| B. | master clear command |
| C. | clear mask register |
| D. | none of the mentioned |
| Answer» C. clear mask register | |
| 2. |
The transfer of a block of data from one set of memory address to another takes place in |
| A. | block transfer mode |
| B. | demand transfer mode |
| C. | memory to memory transfer mode |
| D. | cascade mode |
| Answer» D. cascade mode | |
| 3. |
The mode of 8237 in which the device transfers only one byte per request is |
| A. | block transfer mode |
| B. | single transfer mode |
| C. | demand transfer mode |
| D. | cascade mode |
| Answer» C. demand transfer mode | |
| 4. |
In demand transfer mode of 8237, the device stops data transfer when |
| A. | a TC (terminal count) is reached |
| B. | an external EOP (active low) is detected |
| C. | the DREQ signal goes inactive |
| D. | all of the mentioned |
| Answer» E. | |
| 5. |
To complete a DMA transfer, a memory to memory transfer requires |
| A. | a read from memory cycle |
| B. | a write to memory cycle |
| C. | a read-from and write-to memory cycle |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 6. |
When interface 8237 does not have any valid pending DMA request then it is said to be in |
| A. | active state |
| B. | passive state |
| C. | idle state |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 7. |
The DMA request input pin that has the highest priority is |
| A. | DREQ0 |
| B. | DREQ1 |
| C. | DREQ2 |
| D. | DREQ3 |
| Answer» B. DREQ1 | |
| 8. |
The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is |
| A. | CLEAR |
| B. | SET |
| C. | HLDA |
| D. | RESET |
| Answer» E. | |
| 9. |
The register that keeps track of all the DMA channel pending requests and status of their terminal counts is |
| A. | mask register |
| B. | request register |
| C. | status register |
| D. | count register |
| Answer» D. count register | |
| 10. |
The register that holds the data during memory to memory data transfer is |
| A. | mode register |
| B. | temporary register |
| C. | command register |
| D. | mask register |
| Answer» C. command register | |
| 11. |
Each bit in the request register is cleared by |
| A. | under program control |
| B. | generation of TC |
| C. | generation of an external EOP |
| D. | all of the mentioned |
| Answer» E. | |