MCQOPTIONS
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MCQOPTIONS
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
IF_THE_PIN_LOCK_(ACTIVE_LOW_BASED)_IS_LOW_AT_THE_TRAILING_EDGE_OF_THE_FIRST_ALE_PULSE,_THEN_TILL_THE_START_OF_THE_NEXT_MACHINE_CYCLE,_THE_PIN_LOCK_(ACTIVE_LOW)_IS?$ |
| A. | low |
| B. | high |
| C. | low or high |
| D. | none of the mentioned |
| Answer» B. high | |
| 2. |
With_the_trailing_edge_of_the_LOCK_(active_low),_the_INTA_(active_low)_goes_low_and_remains_in_it_for$ |
| A. | 0 clock cycle |
| B. | 1 clock cycle |
| C. | 2 clock cycles |
| D. | 3 clock cycles |
| Answer» D. 3 clock cycles | |
| 3. |
Once the processor responds to an INTR signal, the IF is automaticall? |
| A. | set |
| B. | reset |
| C. | high |
| D. | low |
| Answer» C. high | |
| 4. |
The status of the pending interrupts is checked at |
| A. | the end of main program |
| B. | the end of all the interrupts executed |
| C. | the beginning of every interrupt |
| D. | the end of each instruction cycle |
| Answer» E. | |
| 5. |
For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in the last clock cycle of the current instruction |
| A. | high |
| B. | low |
| C. | high or low |
| D. | unchanged |
| Answer» B. low | |
| 6. |
The INTR signal can be masked by resetting the |
| A. | TRAP flag |
| B. | INTERRUPT flag |
| C. | MASK flag |
| D. | DIRECTION flag |
| Answer» C. MASK flag | |
| 7. |
The NMI pin should remain high for atleast |
| A. | 4 clock cycles |
| B. | 3 clock cycles |
| C. | 1 clock cycle |
| D. | 2 clock cycles |
| Answer» E. | |
| 8. |
In case of string instructions, the NMI interrupt will be served only after |
| A. | initialisation of string |
| B. | execution of some part of the string |
| C. | complete string is manipulated |
| D. | the occurrence of the interrupt |
| Answer» D. the occurrence of the interrupt | |
| 9. |
The interrupt for which the processor has highest priority among all the internal interrupts is |
| A. | keyboard interrupt |
| B. | TRAP |
| C. | NMI |
| D. | INT |
| Answer» C. NMI | |
| 10. |
The interrupt for which the processor has the highest priority among all the external interrupts is |
| A. | keyboard interrupt |
| B. | TRAP |
| C. | NMI |
| D. | INT |
| Answer» D. INT | |