MCQOPTIONS
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MCQOPTIONS
This section includes 61 Mcqs, each offering curated multiple-choice questions to sharpen your Embedded Systems knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
What is the full form of MESI in Memory Systems? |
| A. | modified exclusive stale invalid |
| B. | modified exclusive shared invalid |
| C. | modified exclusive system input |
| D. | modifies embedded shared invalid |
| Answer» C. modified exclusive system input | |
| 2. |
What are the basic elements required for cache operation? |
| A. | memory array, multivibrator, counter |
| B. | memory array, comparator, counter |
| C. | memory array, trigger circuit, a comparator |
| D. | memory array, comparator, CPU |
| Answer» C. memory array, trigger circuit, a comparator | |
| 3. |
Which configuration of memory organisation replaces By 1 organisation? |
| A. | by 4 organisation |
| B. | by 8 organisation |
| C. | by 9 organisation |
| D. | by 16 organisation |
| Answer» B. by 8 organisation | |
| 4. |
Which is the early form of non-volatile memory? |
| A. | magnetic core memory |
| B. | ferrimagnetic memory |
| C. | anti-magnetic memory |
| D. | anti-ferromagnetic |
| Answer» B. ferrimagnetic memory | |
| 5. |
Which are the two main types of processor connection to the motherboard? |
| A. | sockets and slots |
| B. | sockets and pins |
| C. | slots and pins |
| D. | pins and ports |
| Answer» B. sockets and pins | |
| 6. |
What is the disadvantage of the physical address? |
| A. | debugging |
| B. | delay |
| C. | data preservation |
| D. | data cleared |
| Answer» C. data preservation | |
| 7. |
Which of the following address is seen by the memory unit? |
| A. | logical address |
| B. | physical address |
| C. | virtual address |
| D. | memory address |
| Answer» C. virtual address | |
| 8. |
Which of the following memories has more speed in accessing data? |
| A. | SRAM |
| B. | DRAM |
| C. | EPROM |
| D. | EEPROM |
| Answer» B. DRAM | |
| 9. |
What happens when a task attempts to access memory outside its own address space? |
| A. | paging fault |
| B. | segmentation fault |
| C. | wait |
| D. | remains unchanged |
| Answer» C. wait | |
| 10. |
Which factor determines the cache performance? |
| A. | software |
| B. | peripheral |
| C. | input |
| D. | output |
| Answer» B. peripheral | |
| 11. |
What is the full form of GDTR in Memory Systems? |
| A. | global descriptor table register |
| B. | granularity descriptor table register |
| C. | gate register |
| D. | global direct table register |
| Answer» B. granularity descriptor table register | |
| 12. |
What leads to the development of MESI and MEI protocol? |
| A. | cache size |
| B. | cache coherency |
| C. | bus snooping |
| D. | number of caches |
| Answer» C. bus snooping | |
| 13. |
Which of the following is serial access memory? |
| A. | RAM |
| B. | Flash memory |
| C. | Shifters |
| D. | ROM |
| Answer» D. ROM | |
| 14. |
Which of the memory organisation is widely used in parity bit? |
| A. | by 1 organisation |
| B. | by 4 organisation |
| C. | by 8 organisation |
| D. | by 9 organisation |
| Answer» B. by 4 organisation | |
| 15. |
The modified bit is also known as |
| A. | dead bit |
| B. | neat bit |
| C. | dirty bit |
| D. | invalid bit |
| Answer» D. invalid bit | |
| 16. |
Which of the following support virtual memory? |
| A. | segmentation |
| B. | descriptor |
| C. | selector |
| D. | paging |
| Answer» E. | |
| 17. |
Which of the following have a 16 Mbytes addressed range? |
| A. | PowerPC |
| B. | M68000 |
| C. | DSP56000 |
| D. | TMS 320 |
| Answer» C. DSP56000 | |
| 18. |
What is the purpose of the address bus? |
| A. | to provide data to and from the chip |
| B. | to select a specified chip |
| C. | to select a location within the memory chip |
| D. | to select a read/write cycle |
| Answer» D. to select a read/write cycle | |
| 19. |
What does PMMU stands for? |
| A. | protection mode memory management unit |
| B. | paged memory management unit |
| C. | physical memory management unit |
| D. | paged multiple management unit |
| Answer» C. physical memory management unit | |
| 20. |
What does 'G' in the descriptor entry describe? |
| A. | gain |
| B. | granularity |
| C. | gate voltage |
| D. | global descriptor |
| Answer» C. gate voltage | |
| 21. |
What is the full form of BEDO DRAM in Memory Systems? |
| A. | burst EDO DRAM |
| B. | buffer EDO DRAM |
| C. | BIBO EDO DRAM |
| D. | bilateral EDO DRAM |
| Answer» B. buffer EDO DRAM | |
| 22. |
How many main signals are used with memory chips? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» C. 6 | |
| 23. |
Which mode offers the banking of memory in the DRAM interfacing technique? |
| A. | page mode |
| B. | basic DRAM interfacing |
| C. | page interleaving |
| D. | burst mode |
| Answer» D. burst mode | |
| 24. |
What is the full form of DMA in Memory Systems? |
| A. | direct memory access |
| B. | direct main access |
| C. | data main access |
| D. | data memory address |
| Answer» B. direct main access | |
| 25. |
What type of cache is used in the Intel 80486DX? |
| A. | logical |
| B. | physical |
| C. | harvard |
| D. | unified |
| Answer» E. | |
| 26. |
Which refresh technique is useful for low power consumption? |
| A. | Software refresh |
| B. | CBR |
| C. | RAS |
| D. | Burst refresh |
| Answer» C. RAS | |
| 27. |
Who invented TriMedia processor? |
| A. | Intel |
| B. | IBM |
| C. | Apple |
| D. | NXP Semiconductor |
| Answer» E. | |
| 28. |
What is the full form of TCR in Memory Systems? |
| A. | temperature-compensated refresh |
| B. | temperature-compensated recovery |
| C. | texas CAS-RAS |
| D. | temperature CAS-RAS |
| Answer» B. temperature-compensated recovery | |
| 29. |
Which of the following is a Motorola's protocol product? |
| A. | MCM62940 |
| B. | Avalon |
| C. | Slave interfaces |
| D. | AXI slave interfaces |
| Answer» B. Avalon | |
| 30. |
Which is the very basic technique of refreshing DRAM? |
| A. | refresh cycle |
| B. | burst refresh |
| C. | distributive refresh |
| D. | software refresh |
| Answer» B. burst refresh | |
| 31. |
What is the full form of SIMM in Memory Systems? |
| A. | single in-line memory module |
| B. | single interrupt memory module |
| C. | single information memory module |
| D. | same-in-line memory module |
| Answer» B. single interrupt memory module | |
| 32. |
Why is SRAM more preferably in non-volatile memory? |
| A. | low-cost |
| B. | high-cost |
| C. | low power consumption |
| D. | transistor as a storage element |
| Answer» D. transistor as a storage element | |
| 33. |
Which of the following have an 8 KB page? |
| A. | DEC Alpha |
| B. | ARM |
| C. | VAX |
| D. | PowerPC |
| Answer» B. ARM | |
| 34. |
Which of the following uses a linear line fill interfacing? |
| A. | MC68040 |
| B. | MC68030 |
| C. | US 74707 B2 |
| D. | Hyper Bus |
| Answer» C. US 74707 B2 | |
| 35. |
Which of the following uses a software refresh in the DRAM? |
| A. | 8086 |
| B. | 80386 |
| C. | Pentium |
| D. | Apple II personal computer |
| Answer» E. | |
| 36. |
Which cache memory solve the cache coherency problem? |
| A. | physical cache |
| B. | logical cache |
| C. | unified cache |
| D. | harvard cache |
| Answer» B. logical cache | |
| 37. |
In which memory, the signals are multiplexed? |
| A. | DRAM |
| B. | SRAM |
| C. | EPROM |
| D. | EEPROM |
| Answer» B. SRAM | |
| 38. |
Which of the following has programmable hardware? |
| A. | microcontroller |
| B. | microprocessor |
| C. | coprocessor |
| D. | FPGA |
| Answer» E. | |
| 39. |
What does DPL in the descriptor describes? |
| A. | descriptor page level |
| B. | descriptor privilege level |
| C. | direct page level |
| D. | direct page latch |
| Answer» C. direct page level | |
| 40. |
What is the full form of MEI in Memory Systems? |
| A. | modified embedded invalid |
| B. | modified embedded input |
| C. | modified exclusive invalid |
| D. | modified exclusive input |
| Answer» D. modified exclusive input | |
| 41. |
Which of the following is used to start a supervisor level? |
| A. | error signal |
| B. | default signal |
| C. | wait for the signal |
| D. | interrupt signal |
| Answer» B. default signal | |
| 42. |
Which of the following is necessary for the address translation in the protected mode? |
| A. | descriptor |
| B. | paging |
| C. | segmentation |
| D. | memory |
| Answer» B. paging | |
| 43. |
Which of the following has a fast page mode RAM? |
| A. | burst mode |
| B. | page interleaving |
| C. | EDO memory |
| D. | page mode |
| Answer» D. page mode | |
| 44. |
How many types of tables are used by the processor in the protected mode? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 45. |
Who has invented flash memory? |
| A. | Dr.Fujio Masuoka |
| B. | John Ellis |
| C. | Josh Fisher |
| D. | John Ruttenberg |
| Answer» B. John Ellis | |
| 46. |
Which of the following mode of operation in the DRAM interfacing has a page boundary? |
| A. | burst mode |
| B. | EDO RAM |
| C. | page mode |
| D. | page interleaving |
| Answer» D. page interleaving | |
| 47. |
Which of the following uses a bus snooping mechanism? |
| A. | MC88100 |
| B. | 8086 |
| C. | 8051 |
| D. | 80286 |
| Answer» B. 8086 | |
| 48. |
Which of the following is also known as Illinois protocol? |
| A. | MESI protocol |
| B. | MEI protocol |
| C. | Bus snooping |
| D. | Modified exclusive invalid |
| Answer» B. MEI protocol | |
| 49. |
Which package has high memory speed and change in the supply? |
| A. | DIP |
| B. | SIMM |
| C. | DIMM |
| D. | zig-zag |
| Answer» D. zig-zag | |
| 50. |
Which of the following consist two lines of legs on both sides of a plastic or ceramic body? |
| A. | SIMM |
| B. | DIMM |
| C. | Zig-zag |
| D. | Dual in-line |
| Answer» E. | |