MCQOPTIONS
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MCQOPTIONS
This section includes 11 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
IF_TWO_INTERRUPTS,_OF_HIGHER_PRIORITY_AND_LOWER_PRIORITY_OCCUR_SIMULTANEOUSLY,_THEN_THE_SERVICE_PROVIDED_IS_FOR?$ |
| A. | interrupt of lower priority |
| B. | interrupt of higher priority |
| C. | lower & higher priority interrupts |
| D. | none of the mentioned |
| Answer» C. lower & higher priority interrupts | |
| 2. |
The service to an interrupt will be delayed if it appears during the execution of$ |
| A. | RETI instruction |
| B. | Instruction that writes to IE register |
| C. | Instruction that writes to IP register |
| D. | All of the mentioned |
| Answer» E. | |
| 3. |
For_an_interrupt_to_be_guaranteed_served_it_should_have_duration_of$ |
| A. | one machine cycle |
| B. | three machine cycles |
| C. | two machine cycles |
| D. | four machine cycles |
| Answer» D. four machine cycles | |
| 4. |
The minimum duration of the active low interrupt pulse for being sensed without being lost must b? |
| A. | greater than one machine cycle |
| B. | equal to one machine cycle |
| C. | greater than 2 machine cycles |
| D. | equal to 2 machine cycles |
| Answer» C. greater than 2 machine cycles | |
| 5. |
All the interrupts at level 1 are polled in the second clock cycle of the |
| A. | forth T state |
| B. | fifth T state |
| C. | third T state |
| D. | none |
| Answer» C. third T state | |
| 6. |
The interrupt bit that when set works at level 1, and otherwise at level 0 is |
| A. | PT1 |
| B. | PT0 |
| C. | PX1 |
| D. | All of the mentioned |
| Answer» E. | |
| 7. |
The priority level of an interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is |
| A. | level 0 |
| B. | level 1 |
| C. | level 0 or level 1 |
| D. | none |
| Answer» C. level 0 or level 1 | |
| 8. |
The number of priority levels that each interrupt of 8051 have is |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 9. |
EA bit is used to |
| A. | enable or disable external interrupts |
| B. | enable or disable internal interrupts |
| C. | enable or disable all the interrupts |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 10. |
The bits that control the external interrupts are |
| A. | ET0 and ET1 |
| B. | ET1 and ET2 |
| C. | EX0 and EX1 |
| D. | EX1 and EX2 |
| Answer» D. EX1 and EX2 | |
| 11. |
The external interrupts of 8051 can be enabled by |
| A. | 4 LSBs of TCON register |
| B. | Interrupt enable |
| C. | priority register |
| D. | all of the mentioned |
| Answer» E. | |