MCQOPTIONS
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MCQOPTIONS
This section includes 17 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
THE_UNIT_THAT_PROVIDES_A_FOUR_LEVEL_PROTECTION_MECHANISM,_FOR_SYSTEM‚ÄÖ√Ñ√∂‚ÀÖ√Ë‚ÀÖ¬•S_CODE_AND_DATA_AGAINST_APPLICATION_PROGRAM_IS?$# |
| A. | central processing unit |
| B. | segmentation unit |
| C. | bus interface unit |
| D. | none of the mentioned |
| Answer» C. bus interface unit | |
| 2. |
THE_PAGING_UNIT_WORKS_UNDER_THE_CONTROL_OF?$ |
| A. | memory management unit |
| B. | segmentation unit |
| C. | execution unit |
| D. | instruction unit |
| Answer» C. execution unit | |
| 3. |
The unit that interfaces the internal data bus with the system bus is$ |
| A. | bus sizing unit |
| B. | data buffer |
| C. | bus control unit |
| D. | execution unit |
| Answer» C. bus control unit | |
| 4. |
The unit that has a prioritizer to resolve the priority of the various bus requests is$ |
| A. | bus sizing unit |
| B. | data buffer |
| C. | bus control unit |
| D. | execution unit |
| Answer» D. execution unit | |
| 5. |
The pipeline and dynamic bus sizing units handle |
| A. | data signals |
| B. | address signals |
| C. | control signals |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 6. |
The signal which indicates to the CPU, to fetch a data word for the coprocessor is |
| A. | READY |
| B. | NMI |
| C. | HLDA |
| D. | PEREQ |
| Answer» E. | |
| 7. |
The signal that is used to insert WAIT states in a bus cycle in 80386 is |
| A. | HOLD |
| B. | HLDA |
| C. | READY |
| D. | PEREQ |
| Answer» D. PEREQ | |
| 8. |
Which of the following pin when activated, allows address pipelining? |
| A. | ADS |
| B. | NA |
| C. | AP |
| D. | None of the mentioned |
| Answer» C. AP | |
| 9. |
The unit that drives the bus enable and address signals A0-A31 is |
| A. | bus sizing unit |
| B. | bus driving unit |
| C. | address driver |
| D. | bus driver |
| Answer» D. bus driver | |
| 10. |
The unit that organizes the physical memory, in terms of pages of 4KB size each i? |
| A. | segmentation unit |
| B. | execution unit |
| C. | paging unit |
| D. | instruction unit |
| Answer» D. instruction unit | |
| 11. |
The segmentation unit allows |
| A. | maximum size of 4GB segments |
| B. | use of segment address components |
| C. | use of offset address components |
| D. | all of the mentioned |
| Answer» E. | |
| 12. |
The memory management unit consists of |
| A. | segmentation unit |
| B. | paging unit |
| C. | segmentation and paging units |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 13. |
The unit that increases the speed of all shift and rotate operations is |
| A. | memory management unit |
| B. | execution unit |
| C. | instruction unit |
| D. | barrel shifter |
| Answer» E. | |
| 14. |
The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is |
| A. | memory management unit |
| B. | execution unit |
| C. | instruction unit |
| D. | barrel shifter |
| Answer» D. barrel shifter | |
| 15. |
The unit that is used for handling data, and calculates offset address is |
| A. | memory management unit |
| B. | execution unit |
| C. | instruction unit |
| D. | bus interface unit |
| Answer» C. instruction unit | |
| 16. |
The central processing unit has a sub-division of |
| A. | memory unit and control unit |
| B. | memory unit and ALU |
| C. | execution unit and instruction unit |
| D. | execution unit and memory unit |
| Answer» D. execution unit and memory unit | |
| 17. |
Which of the units is not a part of the internal architecture of 80386? |
| A. | central processing unit |
| B. | memory management unit |
| C. | bus interface unit |
| D. | none of the mentioned |
| Answer» E. | |