MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 14 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
WHAT_IS_ONE_DISADVANTAGE_OF_AN_S-R_FLIP-FLOP??$ |
| A. | It has no Enable input |
| B. | It has a RACE condition |
| C. | It has no clock input |
| D. | None of the Mentioned |
| Answer» E. | |
| 2. |
When is a flip-flop said to be transparent?$ |
| A. | When the Q output is opposite the input |
| B. | When the Q output follows the input |
| C. | When you can see through the IC packaging |
| D. | None of the Mentioned |
| Answer» C. When you can see through the IC packaging | |
| 3. |
One_example_of_the_use_of_an_S-R_flip-flop_is_as:$ |
| A. | Racer |
| B. | Stable oscillator |
| C. | Binary storage register |
| D. | Transition pulse generator |
| Answer» D. Transition pulse generator | |
| 4. |
The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the |
| A. | Edge-detection circuit |
| B. | NOR latch |
| C. | NAND latch |
| D. | Pulse-steering circuit |
| Answer» B. NOR latch | |
| 5. |
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________ |
| A. | SET |
| B. | RESET |
| C. | Clear |
| D. | Invalid |
| Answer» C. Clear | |
| 6. |
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________ |
| A. | The clock pulse is LOW |
| B. | The clock pulse is HIGH |
| C. | The clock pulse transitions from LOW to HIGH |
| D. | The clock pulse transitions from HIGH to LOW |
| Answer» D. The clock pulse transitions from HIGH to LOW | |
| 7. |
The S-R flip flop consist o? |
| A. | 4 AND gates |
| B. | Two additional AND gates |
| C. | An additional clock input |
| D. | None of the Mentioned |
| Answer» C. An additional clock input | |
| 8. |
How many types of flip-flops are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 9. |
The difference between a flip-flop & latch is |
| A. | Both are same |
| B. | Flip-flop consist of an extra output |
| C. | Latches has two inputs but flip-flop has two |
| D. | None of the Mentioned |
| Answer» D. None of the Mentioned | |
| 10. |
The characteristic equation of S-R latch is |
| A. | Q(n+1) = (S + Q(n))R’ |
| B. | Q(n+1) = SR + Q(n)R |
| C. | Q(n+1) = S’R + Q(n)R |
| D. | Q(n+1) = S’R + Q'(n)R |
| Answer» B. Q(n+1) = SR + Q(n)R | |
| 11. |
One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is$ |
| A. | The inputs of NOR latch are 0 but 1 for NAND latch |
| B. | The inputs of NOR latch are 1 but 0 for NAND latch |
| C. | The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch |
| D. | None of the Mentioned |
| Answer» B. The inputs of NOR latch are 1 but 0 for NAND latch | |
| 12. |
A NAND based S’-R’ latch can be converted into S-R latch by placing$ |
| A. | A D latch at each of its input |
| B. | An inverter at each of its input |
| C. | It can never be converted |
| D. | Both a D latch and an inverter at its input |
| Answer» E. | |
| 13. |
In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is:$ |
| A. | No change |
| B. | Set |
| C. | Reset |
| D. | Forbidden |
| Answer» B. Set | |
| 14. |
What is ambiguous condition in a NAND based S’-R’ latch? |
| A. | S’=0, R’=1 |
| B. | S’=1, R’=0 |
| C. | S’=1, R’=1 |
| D. | S’=0, R’=0 |
| Answer» E. | |