Explore topic-wise MCQs in Vlsi.

This section includes 14 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.

1.

The standard unit of capacitance is defined as?

A. Capacitance of gate to channel of MOS transistor having W = L dimensions
B. Capacitance of gate to channel of n-MOS transistor having W = 3L dimensions
C. Capacitance of gate to channel of p-MOS transistor having 3W = L dimensions
D. Capacitance of gate to channel of n-MOS transistor having W = L dimensions and p-MOS having W=3L dimensions
Answer» B. Capacitance of gate to channel of n-MOS transistor having W = 3L dimensions
Discussion
2.

The value of standard unit of capacitance is?

A. 0.01pF
B. 0.0032pF
C. 0.0023pF
D. All of the mentioned
Answer» E.
Discussion
3.

The value of diffusion capacitance in pF x 10-4/ m2 in 2 m design is?

A. 1.75
B. 4
C. 8
D. 16
Answer» D. 16
Discussion
4.

The active capacitance is also called as __________

A. Parasitic capacitance
B. Interconnect capacitance
C. Junction capacitance
D. Diffusion capacitance
Answer» E.
Discussion
5.

The typical value of capacitance in pF x 10-4/ m2 for gate to channel in based design is?

A. 1
B. 0.4
C. 0.2
D. 4
Answer» E.
Discussion
6.

Zero bias depletion capacitance per unit length at sidewall junctions is given by, (Cj is the zero bias depletion capacitance per unit area).

A. ( 10).Cj.xj
B. ( 5).Cj.xj
C. ( 10).Cj.xj<sup>2</sup>
D. ( 10).Cj.xj<sup>3</sup>
Answer» B. ( 5).Cj.xj
Discussion
7.

By what amount is Sidewall doping larger than substrate doping concentration.

A. 5
B. 2
C. 1
D. 10
Answer» E.
Discussion
8.

The amount of gate oxide capacitance is determined by __________

A. Charges present on the gate
B. Polarity of the gate
C. Charges present on the substrate
D. Area of the gate
Answer» E.
Discussion
9.

The interconnect capacitance is formed by __________

A. Area between the interconnect lines
B. Interconnect lines between the gates
C. Inter electrode capacitance of interconnect lines
D. None of the mentioned
Answer» C. Inter electrode capacitance of interconnect lines
Discussion
10.

The total load capacitance is calculated as the sum of __________

A. Drain capacitance in series with input capacitance
B. Drain capacitance + interconnect capacitance +input capacitance
C. Drain capacitance + interconnect capacitance input capacitance
D. Drain capacitance in parallel with input capacitance
Answer» C. Drain capacitance + interconnect capacitance input capacitance
Discussion
11.

The dominant component of the total output capacitance in submicron technology is?

A. Drain diffusion capacitance
B. Gate oxide capacitance
C. Interconnect capacitance
D. Junction parasitic capacitance
Answer» D. Junction parasitic capacitance
Discussion
12.

The amount of parasitic capacitance at the output node is determined by __________

A. Concentration of the impurity doped
B. Size of the total drain diffusion area
C. Charges stored in the capacitor
D. None of the mentioned
Answer» C. Charges stored in the capacitor
Discussion
13.

The junction parasitic capacitance are produced due to ____________

A. Source diffusion regions
B. Gate diffusion regions
C. Drain diffusion region
D. All of the mentioned
Answer» D. All of the mentioned
Discussion
14.

Which of the following mainly constitutes the output node capacitance?

A. Inter electrode capacitance
B. Stray capacitance
C. Junction Parasitic capacitance
D. All of the mentioned
Answer» D. All of the mentioned
Discussion