MCQOPTIONS
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MCQOPTIONS
This section includes 14 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
When both inputs of SR latches are high, the latch goes ___________ |
| A. | Unstable |
| B. | Stable |
| C. | Metastable |
| D. | Bistable |
| Answer» D. Bistable | |
| 2. |
When both inputs of SR latches are low, the latch ___________ |
| A. | Q output goes high |
| B. | Q output goes high |
| C. | It remains in its previously set or reset state |
| D. | it goes to its next set or reset state |
| Answer» D. it goes to its next set or reset state | |
| 3. |
When a high is applied to the Set line of an SR latch, then ___________ |
| A. | Q output goes high |
| B. | Q output goes high |
| C. | Q output goes low |
| D. | Both Q and Q go high |
| Answer» B. Q output goes high | |
| 4. |
The inputs of SR latch are ___________ |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | j and k |
| Answer» D. j and k | |
| 5. |
The first step of the analysis procedure of SR latch is to ___________ |
| A. | label inputs |
| B. | label outputs |
| C. | label states |
| D. | label tables |
| Answer» C. label states | |
| 6. |
The NAND latch works when both inputs are ___________ |
| A. | 1 |
| B. | 0 |
| C. | Inverted |
| D. | Don t cares |
| Answer» B. 0 | |
| 7. |
The outputs of SR latch are ___________ |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | q and q |
| Answer» E. | |
| 8. |
The SR latch consists of ___________ |
| A. | 1 input |
| B. | 2 inputs |
| C. | 3 inputs |
| D. | 4 inputs |
| Answer» C. 3 inputs | |
| 9. |
The full form of SR is ___________ |
| A. | System rated |
| B. | Set reset |
| C. | Set ready |
| D. | Set Rated |
| Answer» C. Set ready | |
| 10. |
How many types of latches are ___________ |
| A. | 4 |
| B. | 3 |
| C. | 2 |
| D. | 5 |
| Answer» B. 3 | |
| 11. |
Two stable states of latches are ___________ |
| A. | Astable & Monostable |
| B. | Low input & high output |
| C. | High output & low output |
| D. | Low output & high input |
| Answer» D. Low output & high input | |
| 12. |
Why latches are called memory devices? |
| A. | It has capability to stare 8 bits of data |
| B. | It has internal memory of 4 bit |
| C. | It can store one bit of data |
| D. | It can store infinite amount of data |
| Answer» D. It can store infinite amount of data | |
| 13. |
Latch is a device with ___________ |
| A. | One stable state |
| B. | Two stable state |
| C. | Three stable state |
| D. | Infinite stable states |
| Answer» C. Three stable state | |
| 14. |
A latch is an example of a ___________ |
| A. | Monostable multivibrator |
| B. | Astable multivibrator |
| C. | Bistable multivibrator |
| D. | 555 timer |
| Answer» D. 555 timer | |