Explore topic-wise MCQs in Computer Organization.

This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.

1.

The instruction, ADD R1, R2, R3 is decoded as ___________

A. R1<-[R1]+[R2]+[R3]
B. R3<-[R1]+[R2]
C. R3<-[R1]+[R2]+[R3]
D. R1<-[R2]+[R3]
Answer» E.
Discussion
2.

The Bit extension of the register is denoted with the help of __________ symbol.

A. $
B. `
C. E
D. ~
Answer» D. ~
Discussion
3.

The register used to serve as PC is called as ___________

A. Indirection register
B. Instruction pointer
C. R-32
D. None of the mentioned
Answer» C. R-32
Discussion
4.

In IA-32 architecture along with the general flags, the other conditional flags provided are ___________

A. IOPL
B. IF
C. TF
D. All of the mentioned
Answer» E.
Discussion
5.

IOPL stands for ________

A. Input/Output Privilege level
B. Input Output Process Link
C. Internal Output Process Link
D. Internal Offset Privilege Level
Answer» B. Input Output Process Link
Discussion
6.

The IA-32 architecture associates different parts of memory called __________ with different usages.

A. Frames
B. Pages
C. Tables
D. Segments
Answer» E.
Discussion
7.

The size of the floating registers can be extended upto _________

A. 128 bit
B. 256 bit
C. 80 bit
D. 64 bit
Answer» D. 64 bit
Discussion
8.

The Floating point registers of IA-32 can operate on operands up to ___________

A. 128 bit
B. 256 bit
C. 80 bit
D. 64 bit
Answer» E.
Discussion
9.

The addressing method used in IA-32 is ____________

A. Little Endian
B. Big Endian
C. X-Little Endian
D. Both Little and Big Endian
Answer» B. Big Endian
Discussion
10.

The address space of the IA-32 is __________

A. 2<sup>16</sup>
B. 2<sup>32</sup>
C. 2<sup>64</sup>
D. 2<sup>8</sup>
Answer» C. 2<sup>64</sup>
Discussion