MCQOPTIONS
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MCQOPTIONS
This section includes 13 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
For a pseudo nMOS design the impedance of pull up and pull down ratio is |
| A. | 4:1 |
| B. | 1:4 |
| C. | 3:1 |
| D. | 1:3 |
| Answer» D. 1:3 | |
| 2. |
BiCMOS is used for ____ fan-out. |
| A. | less |
| B. | more |
| C. | no |
| D. | very less |
| Answer» C. no | |
| 3. |
The CMOS inverter has _____ power dissipation. |
| A. | low |
| B. | more |
| C. | no |
| D. | very less |
| Answer» D. very less | |
| 4. |
FOR_A_PSEUDO_NMOS_DESIGN_THE_IMPEDANCE_OF_PULL_UP_AND_PULL_DOWN_RATIO_IS?$ |
| A. | 4:1 |
| B. | 1:4 |
| C. | 3:1 |
| D. | 1:3 |
| Answer» D. 1:3 | |
| 5. |
Which gate is faster? |
| A. | AND |
| B. | NAND |
| C. | NOR |
| D. | OR |
| Answer» D. OR | |
| 6. |
Which can handle high capacitance load? |
| A. | NAND |
| B. | nMOS NAND |
| C. | CMOS NAND |
| D. | BiCMOS NAND |
| Answer» E. | |
| 7. |
BiCMOS is used for ____ fan-out |
| A. | less |
| B. | more |
| C. | no |
| D. | very less |
| Answer» C. no | |
| 8. |
In CMOS NAND gate, p transistors are connected in |
| A. | series |
| B. | parallel |
| C. | cascade |
| D. | random |
| Answer» C. cascade | |
| 9. |
NAND gate delay can be given as |
| A. | Ʈint |
| B. | Ʈint/n |
| C. | n*Ʈint |
| D. | 2n*Ʈint |
| Answer» D. 2n*‚Äö√†√ú‚àö√úint | |
| 10. |
As the number of inputs increases, the NAND gate delay |
| A. | increases |
| B. | decreases |
| C. | does not vary |
| D. | exponentially decreases |
| Answer» B. decreases | |
| 11. |
The CMOS inverter has _____ power dissipation |
| A. | low |
| B. | more |
| C. | no |
| D. | very less |
| Answer» D. very less | |
| 12. |
Both NAND and NOR gates can be used in gate logic. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 13. |
Gate logic is also called as |
| A. | transistor logic |
| B. | switch logic |
| C. | complementary logic |
| D. | restoring logic |
| Answer» E. | |