MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 161 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 151. |
In a 555 timer, three 5 k resistors provide a trigger level of ________. |
| A. | 1/4 VCC and a threshold level 1/2 VCC |
| B. | 1/3 VCC and a threshold level 3/4 VCC |
| C. | 1/3 VCC and a threshold level 2/3 VCC |
| D. | 1/4 VCC and a threshold level 2/3 VCC |
| Answer» D. 1/4 VCC and a threshold level 2/3 VCC | |
| 152. |
The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs. |
| A. | PRE, CLR, LOW |
| B. | ON, OFF, HIGH |
| C. | START, STOP, LOW |
| D. | SET, RESET, HIGH |
| Answer» B. ON, OFF, HIGH | |
| 153. |
How is a J-K flip-flop made to toggle? |
| A. | J = 0, K = 0 |
| B. | J = 1, K = 0 |
| C. | J = 0, K = 1 |
| D. | J = 1, K = 1 |
| Answer» E. | |
| 154. |
How many flip-flops are in the 7475 IC? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» D. 8 | |
| 155. |
A 555 timer is connected for astable operation as shown below along with the output waveform. It is determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while maintaining the same output frequency? |
| A. | Increase the value of C. |
| B. | Increase Vcc and decrease RL. |
| C. | Decrease R1 and R2. |
| D. | Decrease R1 and increase R2. |
| Answer» E. | |
| 156. |
Which is not an Altera primitive port identifier? |
| A. | clk |
| B. | ena |
| C. | clr |
| D. | prn |
| Answer» D. prn | |
| 157. |
Propagation delay time, tPLH, is measured from the ________. |
| A. | triggering edge of the clock pulse to the LOW-to-HIGH transition of the output |
| B. | triggering edge of the clock pulse to the HIGH-to-LOW transition of the output |
| C. | preset input to the LOW-to-HIGH transition of the output |
| D. | clear input to the HIGH-to-LOW transition of the output |
| Answer» B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output | |
| 158. |
What is the hold condition of a flip-flop? |
| A. | both S and R inputs activated |
| B. | no active S or R input |
| C. | only S is active |
| D. | only R is active |
| Answer» C. only S is active | |
| 159. |
In VHDL, in which declaration section is a COMPONENT declared? |
| A. | Architecture |
| B. | Library |
| C. | Entity |
| D. | Port map |
| Answer» B. Library | |
| 160. |
Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? |
| A. | The logic level at the D input is transferred to Q on NGT of CLK. |
| B. | The Q output is ALWAYS identical to the CLK input if the D input is HIGH. |
| C. | The Q output is ALWAYS identical to the D input when CLK = PGT. |
| D. | The Q output is ALWAYS identical to the D input. |
| Answer» B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH. | |
| 161. |
Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. |
| A. | 10.24 kHz |
| B. | 5 kHz |
| C. | 30.24 kHz |
| D. | 15 kHz |
| Answer» C. 30.24 kHz | |