Explore topic-wise MCQs in Digital Electronics.

This section includes 161 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Electronics knowledge and support exam preparation. Choose a topic below to get started.

101.

In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.

A. 1
B.
C. 1
D.
Answer» C. 1
Discussion
102.

Which of the following is correct for a D latch?

A. The output toggles if one of the inputs is held HIGH.
B. Q output follows the input D when the enable is HIGH.
C. Only one of the inputs can be HIGH at a time.
D. The output complement follows the input when enabled.
Answer» C. Only one of the inputs can be HIGH at a time.
Discussion
103.

The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

A. opposite, active clock edge
B. inverted, positive clock edge
C. quiescent, negative clock edge
D. reset, synchronous clock edge
Answer» B. inverted, positive clock edge
Discussion
104.

The key to edge-triggered sequential circuits in VHDL is the ________.

A. ARCHITECTURE
B. PROCESS
C. FUNCTION
D. VARIABLE
Answer» C. FUNCTION
Discussion
105.

The symbols on this flip-flop device indicate ________.

A. triggering takes place on the negative-going edge of the CLK pulse
B. triggering takes place on the positive-going edge of the CLK pulse
C. triggering can take place anytime during the HIGH level of the CLK waveform
D. triggering can take place anytime during the LOW level of the CLK waveform
Answer» B. triggering takes place on the positive-going edge of the CLK pulse
Discussion
106.

A D latch has one data-input line.

A. 1
B.
C. 1
D.
Answer» B.
Discussion
107.

A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

A. CLK = NGT, D = 0
B. CLK = PGT, D = 0
C. CLOCK NGT, D = 1
D. CLOCK PGT, D = 1
Answer» E.
Discussion
108.

The term CLEAR always means that .

A. 1
B.
Answer» B.
Discussion
109.

Which of the following is correct for a gated D flip-flop?

A. The output toggles if one of the inputs is held HIGH.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D. Q output follows the input D when the enable is HIGH.
Answer» E.
Discussion
110.

When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.

A. be invalid
B. not change
C. remain unchanged
D. toggle
Answer» E.
Discussion
111.

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

A. 16
B. 8
C. 4
D. 2
Answer» C. 4
Discussion
112.

The output pulse width for a 555 monostable circuit with R1 = 3.3 k and C1 = 0.02 F is ________.

A. 7.3 s
B. 73 s
C. 7.3 ms
D. 73 ms
Answer» C. 7.3 ms
Discussion
113.

PRESET and CLEAR inputs are normally synchronous.

A. 1
B.
Answer» C.
Discussion
114.

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

A. the clock pulse is LOW
B. the clock pulse is HIGH
C. the clock pulse transitions from LOW to HIGH
D. the clock pulse transitions from HIGH to LOW
Answer» D. the clock pulse transitions from HIGH to LOW
Discussion
115.

Which is not a real advantage of HDL?

A. Using higher levels of abstraction
B. Tailoring components to exactly fit the needs of the project
C. The use of graphical tools
D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project
Answer» D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project
Discussion
116.

What is another name for a one-shot?

A. Monostable
B. Multivibrator
C. Bistable
D. Astable
Answer» B. Multivibrator
Discussion
117.

The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

A. edge-detection circuit.
B. NOR latch.
C. NAND latch.
D. pulse-steering circuit.
Answer» B. NOR latch.
Discussion
118.

VHDL does require a special designation for an output with a feedback.

A. 1
B.
Answer» B.
Discussion
119.

The output pulse width of a 555 monostable circuit with R1 = 4.7 k and C1 = 47 F is ________.

A. 24 s
B. 24 ms
C. 243 ms
D. 243 s
Answer» D. 243 s
Discussion
120.

Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.

A. set
B. reset
C. latch
D. toggle
Answer» E.
Discussion
121.

A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?

A. The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
B. The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
C. A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
D. A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.
Answer» E.
Discussion
122.

VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code without relying on logic primitives.

A. 1
B.
C. 1
D.
Answer» B.
Discussion
123.

What is one disadvantage of an S-R flip-flop?

A. It has no enable input.
B. It has an invalid state.
C. It has no clock input.
D. It has only a single output.
Answer» C. It has no clock input.
Discussion
124.

What is the difference between the 7476 and the 74LS76?

A. the 7476 is master-slave, the 74LS76 is master-slave
B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
C. the 7476 is edge-triggered, the 74LS76 is master-slave
D. the 7476 is master-slave, the 74LS76 is edge-triggered
Answer» E.
Discussion
125.

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

A. clock is LOW
B. slave is transferring
C. flip-flop is reset
D. clock is HIGH
Answer» E.
Discussion
126.

The pulse width of a one-shot circuit is determined by ________.

A. a resistor and capacitor
B. two resistors
C. two capacitors
D. none of the above
Answer» B. two resistors
Discussion
127.

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

A. SET
B. RESET
C. clear
D. invalid
Answer» C. clear
Discussion
128.

Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.

A. 1
B.
C. 1
D.
Answer» B.
Discussion
129.

If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

A. An invalid state will exist.
B. No change will occur in the output.
C. The output will toggle.
D. The output will reset.
Answer» C. The output will toggle.
Discussion
130.

On a J-K flip-flop, when is the flip-flop in a hold condition?

A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer» B. J = 1, K = 0
Discussion
131.

Why are the S and R inputs of a gated flip-flop said to be synchronous?

A. They must occur with the gate.
B. They occur independent of the gate.
Answer» B. They occur independent of the gate.
Discussion
132.

When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.

A. S = 1, R = 1
B. S = 1, R = 0
C. S = 0, R = 1
D. S = 0, R = 0
Answer» E.
Discussion
133.

In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.

A. traffic
B. D
C. flip-flop
D. clock
Answer» E.
Discussion
134.

What does the triangle on the clock input of a J-K flip-flop mean?

A. level enabled
B. edge-triggered
Answer» C.
Discussion
135.

An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 k and a CEXT of 0.005 F. The pulse width is ________.

A. 70 s
B. 16 s
C. 160 s
D. 32 s
Answer» D. 32 s
Discussion
136.

The ________ is the time interval immediately following the active transition of the clock signal.

A. hold time
B. setup time
C. over-time
D. hang-time
Answer» B. setup time
Discussion
137.

With regard to a D latch, ________.

A. the Q output follows the D input when EN is LOW
B. the Q output is opposite the D input when EN is LOW
C. the Q output follows the D input when EN is HIGH
D. the Q output is HIGH regardless of EN's input state
Answer» D. the Q output is HIGH regardless of EN's input state
Discussion
138.

In VHDL, how is each instance of a component addressed?

A. A name followed by a colon and the name of the library primitive
B. A name followed by a semicolon and the component type
C. A name followed by the library being used
D. A name followed by the component library number
Answer» B. A name followed by a semicolon and the component type
Discussion
139.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

A. cross coupling
B. gate impedance
C. low input voltages
D. asynchronous operation
Answer» B. gate impedance
Discussion
140.

Which of the following is not generally associated with flip-flops?

A. Hold time
B. Propagation delay time
C. Interval time
D. Set up time
Answer» D. Set up time
Discussion
141.

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

A. constantly LOW
B. constantly HIGH
C. a 20 kHz square wave
D. a 10 kHz square wave
Answer» E.
Discussion
142.

Which of the following describes the operation of a positive edge-triggered D flip-flop?

A. If both inputs are HIGH, the output will toggle.
B. The output will follow the input on the leading edge of the clock.
C. When both inputs are LOW, an invalid state exists.
D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Answer» C. When both inputs are LOW, an invalid state exists.
Discussion
143.

A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.

A. 1
B.
C. 1
D.
Answer» B.
Discussion
144.

How many flip-flops are required to produce a divide-by-128 device?

A. 1
B. 4
C. 6
D. 7
Answer» E.
Discussion
145.

To completely load and then unload an 8-bit register requires how many clock pulses?

A. 2
B. 4
C. 8
D. 16
Answer» E.
Discussion
146.

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.

A. 1
B.
C. Using higher levels of abstraction
D. Tailoring components to exactly fit the needs of the project
Answer» C. Using higher levels of abstraction
Discussion
147.

Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.

A. The circuit is functioning properly.
B. Q2 is incorrect; the flip-flop is probably bad.
C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
D. A bad connection probably exists between FF-3 and FF-4, causing FF-3 not to reset.
Answer» C. The input to flip-flop 3 (D2) is probably wrong; check the source of D2.
Discussion
148.

Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.

A. 1
B.
C. Hold time
D. Propagation delay time
Answer» C. Hold time
Discussion
149.

Edge-triggered flip-flops must have:

A. very fast response times.
B. at least two inputs to handle rising and falling edges.
C. a pulse transition detector.
D. active-LOW inputs and complemented outputs.
Answer» D. active-LOW inputs and complemented outputs.
Discussion
150.

One example of the use of an S-R flip-flop is as a(n):

A. racer
B. astable oscillator
C. binary storage register
D. transition pulse generator
Answer» D. transition pulse generator
Discussion