MCQOPTIONS
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MCQOPTIONS
This section includes 27 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of __________ |
| A. | ECL |
| B. | VECL |
| C. | PECL |
| D. | LECL |
| Answer» D. LECL | |
| 2. |
The ECL circuits usually operates with __________ |
| A. | Negative voltage |
| B. | Positive voltage |
| C. | Grounded voltage |
| D. | High Voltage |
| Answer» B. Positive voltage | |
| 3. |
At the time of invention, an ECL was called as __________ |
| A. | Source-coupled logic |
| B. | Current Mode Logic |
| C. | Current-steering logic |
| D. | Emitter-coupled logic |
| Answer» D. Emitter-coupled logic | |
| 4. |
ECL was invented in _______ by __________ |
| A. | 1956, Baker clamp |
| B. | 1976, James R. Biard |
| C. | 1956, Hannon S. Yourke |
| D. | 1976, Yourke |
| Answer» D. 1976, Yourke | |
| 5. |
The equivalent of emitter-coupled logic made out of FETs is called __________ |
| A. | CML |
| B. | SCFL |
| C. | FECL |
| D. | EFCL |
| Answer» C. FECL | |
| 6. |
The full form of SCFL is __________ |
| A. | Source-collector logic |
| B. | Source-coupled logic |
| C. | Source-complementary logic |
| D. | Source Cored Logic |
| Answer» C. Source-complementary logic | |
| 7. |
ECL’s major disadvantage is that __________ |
| A. | It requires more power |
| B. | It’s fanout capability is high |
| C. | It creates more noise |
| D. | It is slow |
| Answer» B. It’s fanout capability is high | |
| 8. |
In ECL the fanout capability is __________ |
| A. | High |
| B. | Low |
| C. | Zero |
| D. | Sometimes high and sometimes low |
| Answer» B. Low | |
| 9. |
The ECL behaves as __________ |
| A. | NOT gate |
| B. | NOR gate |
| C. | NAND gate |
| D. | AND gate |
| Answer» C. NAND gate | |
| 10. |
In an ECL the output is taken from __________ |
| A. | Emitter |
| B. | Base |
| C. | Collector |
| D. | Junction of emitter and base |
| Answer» D. Junction of emitter and base | |
| 11. |
Sometimes ECL can also be named as __________ |
| A. | EEL |
| B. | CEL |
| C. | CML |
| D. | CCL |
| Answer» D. CCL | |
| 12. |
The full form of CML is __________ |
| A. | Complementary mode logic |
| B. | Current mode logic |
| C. | Collector mode logic |
| D. | Collector Mixed Logic |
| Answer» D. Collector Mixed Logic | |
| 13. |
The full form of ECL is __________ |
| A. | Emitter-collector logic |
| B. | Emitter-complementary logic |
| C. | Emitter-coupled logic |
| D. | Emitter-cored logic |
| Answer» D. Emitter-cored logic | |
| 14. |
THE_FULL_FORM_OF_SCFL_IS?$ |
| A. | Source-collector logic |
| B. | Source-coupled logic |
| C. | Source-complementary logic |
| D. | None of the Mentioned |
| Answer» C. Source-complementary logic | |
| 15. |
ECL was invented in _______ by __________$ |
| A. | 1956, Baker clamp |
| B. | 1976, James R. Biard |
| C. | 1956, Hannon S. Yourke |
| D. | 1976, Yourke |
| Answer» D. 1976, Yourke | |
| 16. |
The equivalent of emitter-coupled logic made out of FETs is called$ |
| A. | CML |
| B. | SCFL |
| C. | FECL |
| D. | EFCL |
| Answer» C. FECL | |
| 17. |
Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of |
| A. | ECL |
| B. | VECL |
| C. | PECL |
| D. | LECL |
| Answer» D. LECL | |
| 18. |
The ECL circuits usually operates with |
| A. | Negative voltage |
| B. | Positive voltage |
| C. | Grounded voltage |
| D. | None of the Mentioned |
| Answer» B. Positive voltage | |
| 19. |
At the time of invention, an ECL was called as |
| A. | Source-coupled logic |
| B. | Current Mode Logic |
| C. | Current-steering logic |
| D. | Emitter-coupled logic |
| Answer» D. Emitter-coupled logic | |
| 20. |
ECL’s major disadvantage is tha?# |
| A. | It requires more power |
| B. | It’s fanout capability is high |
| C. | It creates more noise |
| D. | None of the Mentioned |
| Answer» B. It‚Äö√Ñ√∂‚àö√ë‚àö¬•s fanout capability is high | |
| 21. |
In ECL the fanout capability is |
| A. | High |
| B. | Low |
| C. | Zero |
| D. | Sometimes high and sometimes low |
| Answer» B. Low | |
| 22. |
The ECL behaves as |
| A. | NOT gate |
| B. | NOR gate |
| C. | NAND gate |
| D. | AND gate |
| Answer» C. NAND gate | |
| 23. |
In an ECL the output is taken from |
| A. | Emitter |
| B. | Base |
| C. | Collector |
| D. | None of the Mentioned |
| Answer» D. None of the Mentioned | |
| 24. |
Sometimes ECL can also be named as |
| A. | EEL |
| B. | CEL |
| C. | CML |
| D. | CCL |
| Answer» D. CCL | |
| 25. |
The full form of CML is |
| A. | Complementary mode logic |
| B. | Current mode logic |
| C. | Collector mode logic |
| D. | None of the Mentioned |
| Answer» D. None of the Mentioned | |
| 26. |
Which logic is the fastest of all the logic families? |
| A. | TTL |
| B. | ECL |
| C. | HTL |
| D. | DTL |
| Answer» C. HTL | |
| 27. |
The full form of ECL is |
| A. | Emitter-collector logic |
| B. | Emitter-complementary logic |
| C. | Emitter-coupled logic |
| D. | None of the Mentioned |
| Answer» D. None of the Mentioned | |