MCQOPTIONS
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MCQOPTIONS
This section includes 15 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
THE_TECHNIQUE_WHEREBY_THE_DMA_CONTROLLER_STEALS_THE_ACCESS_CYCLES_OF_THE_PROCESSOR_TO_OPERATE_IS_CALLED?$ |
| A. | Fast conning |
| B. | Memory Con |
| C. | Cycle stealing |
| D. | Memory stealing |
| Answer» D. Memory stealing | |
| 2. |
The controller uses _____ to help with the transfers when handling network interfaces.$ |
| A. | Input Buffer storage |
| B. | Signal enhancers |
| C. | Bridge circuits |
| D. | All of the mentioned |
| Answer» B. Signal enhancers | |
| 3. |
The_technique_where_the_controller_is_given_complete_access_to_main_memory_is$ |
| A. | Cycle stealing |
| B. | Memory stealing |
| C. | Memory Con |
| D. | Burst mode |
| Answer» E. | |
| 4. |
The DMA transfer is initiated by _____ |
| A. | Processor |
| B. | The process being executed |
| C. | I/O devices |
| D. | OS |
| Answer» D. OS | |
| 5. |
When the process requests for a DMA transfer |
| A. | Then the process is temporarily suspended |
| B. | The process continues execution |
| C. | Another process gets executed |
| D. | process is temporarily suspended & Another process gets executed |
| Answer» E. | |
| 6. |
The registers of the controller are ______ |
| A. | 64 bits |
| B. | 24 bits |
| C. | 32 bits |
| D. | 16 bits |
| Answer» D. 16 bits | |
| 7. |
To_overcome_the_conflict_over_the_possession_of_the_BUS_we_use_______ |
| A. | Optimizers |
| B. | BUS arbitrators |
| C. | Multiple BUS structure |
| D. | None of the mentioned |
| Answer» C. Multiple BUS structure | |
| 8. |
Can a single DMA controller perform operations on two different disks simultaneously? |
| A. | True |
| B. | False |
| Answer» B. False | |
| 9. |
The controller is connected to the ____ |
| A. | Processor BUS |
| B. | System BUS |
| C. | External BUS |
| D. | None of the mentioned |
| Answer» C. External BUS | |
| 10. |
When the R/W bit of the status register of the DMA controller is set to 1. |
| A. | Read operation is performed |
| B. | Write operation is performed |
| C. | Read & Write operation is performed |
| D. | None of the mentioned |
| Answer» B. Write operation is performed | |
| 11. |
The DMA controller has _______ registers |
| A. | 4 |
| B. | 2 |
| C. | 3 |
| D. | 1 |
| Answer» D. 1 | |
| 12. |
After the completion of the DMA transfer, the processor is notified by |
| A. | Acknowledge signal |
| B. | Interrupt signal |
| C. | WMFC signal |
| D. | None of the mentioned |
| Answer» C. WMFC signal | |
| 13. |
In DMA transfers, the required signals and addresses are given by the |
| A. | Processor |
| B. | Device drivers |
| C. | DMA controllers |
| D. | The program itself |
| Answer» D. The program itself | |
| 14. |
The DMA transfers are performed by a control circuit called as |
| A. | Device interface |
| B. | DMA controller |
| C. | Data controller |
| D. | Overlooker |
| Answer» C. Data controller | |
| 15. |
The DMA differs from the interrupt mode by |
| A. | The involvement of the processor for the operation |
| B. | The method of accessing the I/O devices |
| C. | The amount of data transfer possible |
| D. | None of the mentioned |
| Answer» E. | |