2291 + Mcqs in Digital Electronics Page 7 McqOptions

301.	The problem of interfacing IC logic families that have different supply voltages (VCC's) can be solved by using a:
A.	level-shifter
B.	tristate shifter
C.	decoupling capacitor
D.	pull-down resistor
Answer» B. tristate shifter

Discussion

302.	The term buffer/driver signifies the ability to provide low output currents to drive light loads.
A.	True
B.	False
Answer» C.

Discussion

303.	Why is the operating frequency for CMOS devices critical for determining power dissipation?
A.	At low frequencies, power dissipation increases.
B.	At high frequencies, the gate will only be able to deliver 70.7 % of rated power.
C.	At high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.
D.	At high frequencies, the gate will only be able to deliver 70.7 % of rated power and charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.
Answer» D. At high frequencies, the gate will only be able to deliver 70.7 % of rated power and charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation.

Discussion

304.	The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:
A.	a CMOS inverting bilateral switch between the stages
B.	a TTL tristate inverting buffer between the stages
C.	a CMOS noninverting bilateral switch between the stages
D.	a CMOS buffer or inverting buffer
Answer» E.

Discussion

305.	Which family of devices has the characteristic of preventing saturation during operation?
A.	TTL
B.	MOS
C.	ECL
D.	IIL
Answer» D. IIL

Discussion

306.	How many 74LSTTL logic gates can be driven from a 74TTL gate?
A.	10
B.	20
C.	200
D.	400
Answer» C. 200

Discussion

307.	From the following specifications determine the fan-out for the logic family.
A.	HIGH state is 16, LOW state is 8
B.	HIGH state is 8, LOW state is 16
C.	HIGH state is 4, LOW state is 8
D.	HIGH state is 8, LOW state is 4
Answer» C. HIGH state is 4, LOW state is 8

Discussion

308.	CLB is the acronym for ________.
A.	Configurable Logic Block
B.	Configurable Logic Buffer
C.	Critical Logic Buffer
D.	Constant Logic Buffer
Answer» B. Configurable Logic Buffer

Discussion

309.	What can the GAL22V10 do that the GAL16V8 cannot?
A.	It has an extra-large array.
B.	It is in-system programmable.
C.	It has twice the special function pins.
D.	All of the above
Answer» C. It has twice the special function pins.

Discussion

310.	The output of this circuit is always ________.
A.	1
B.	0
C.	A
D.	<span style="text-decoration:overline">A</span>
Answer» E.

Discussion

311.	By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible.
A.	PAL
B.	PLA
C.	CPLD
D.	EEPROM
Answer» B. PLA

Discussion

312.	Now many times can a GAL be erased and reprogrammed?
A.	0
B.	At least 100
C.	At least 1000
D.	Over 10,000
Answer» C. At least 1000

Discussion

313.	Which of the following increases the number of product terms by borrowing unused product from other macrocells?
A.	Shared expander
B.	Parallel expander
C.	Series expander
D.	Slice expander
Answer» C. Series expander

Discussion

314.	MPGA stands for:
A.	mass produced gated array.
B.	Morgan-Phillips gated array.
C.	memory programmed ROM.
D.	mask programmed ROM.
Answer» E.

Discussion

315.	Which of the figures shown below represents the exclusive-NOR gate?
A.	a
B.	b
C.	c
D.	d
Answer» C. c

Discussion

316.	For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output?
A.	LOW
B.	HIGH
C.	Don't Care
D.	Cannot be determined
Answer» B. HIGH

Discussion

317.	Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?
A.	a
B.	b
C.	c
D.	d
Answer» E.

Discussion

318.	For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH. What is the status of the Y output?
A.	LOW
B.	HIGH
C.	Don't Care
D.	Cannot be determined
Answer» B. HIGH

Discussion

319.	Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
A.	True
B.	False
Answer» C.

Discussion

320.	Which of the following is not generally associated with flip-flops?
A.	Hold time
B.	Propagation delay time
C.	Interval time
D.	Set up time
Answer» D. Set up time

Discussion

321.	What is one disadvantage of an S-R flip-flop?
A.	It has no enable input.
B.	It has an invalid state.
C.	It has no clock input.
D.	It has only a single output.
Answer» C. It has no clock input.

Discussion

322.	Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
A.	active-HIGH
B.	active-LOW
Answer» B. active-LOW

Discussion

323.	The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
A.	edge-detection circuit.
B.	NOR latch.
C.	NAND latch.
D.	pulse-steering circuit.
Answer» B. NOR latch.

Discussion

324.	With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
A.	16
B.	8
C.	4
D.	2
Answer» C. 4

Discussion

325.	One example of the use of an S-R flip-flop is as a(n):
A.	racer
B.	astable oscillator
C.	binary storage register
D.	transition pulse generator
Answer» D. transition pulse generator

Discussion

326.	A J-K flip-flop is in a "no change" condition when ________.
A.	J = 1, K = 1
B.	J = 1, K = 0
C.	J = 0, K = 1
D.	J = 0, K = 0
Answer» E.

Discussion

327.	What is the difference between the 7476 and the 74LS76?
A.	the 7476 is master-slave, the 74LS76 is master-slave
B.	the 7476 is edge-triggered, the 74LS76 is edge-triggered
C.	the 7476 is edge-triggered, the 74LS76 is master-slave
D.	the 7476 is master-slave, the 74LS76 is edge-triggered
Answer» E.

Discussion

328.	Which is not an Altera primitive port identifier?
A.	clk
B.	ena
C.	clr
D.	prn
Answer» D. prn

Discussion

329.	The timing network that sets the output frequency of a 555 astable circuit contains ________.
A.	three external resistors are used
B.	two external resistors and an external capacitor are used
C.	an external resistor and two external capacitors are used
D.	no external resistor or capacitor is required
Answer» C. an external resistor and two external capacitors are used

Discussion

330.	MOD-6 and MOD-12 counters and multiples are most commonly used as:
A.	frequency counters
B.	multiplexed displays
C.	digital clocks
D.	power consumption meters
Answer» D. power consumption meters

Discussion

331.	Which of the following is an invalid state in an 8421 BCD counter?
A.	0011
B.	1001
C.	1000
D.	1100
Answer» E.

Discussion

332.	After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?
A.	0,1,0,1,1
B.	1,1,0,1,0
C.	1,0,1,0,1
D.	0,0,0,0,0
Answer» E.

Discussion

333.	How many different states does a 2-bit asynchronous counter have?
A.	1
B.	2
C.	4
D.	8
Answer» D. 8

Discussion

334.	Which of the following statements are true?
A.	Asynchronous events do not occur at the same time.
B.	Asynchronous events are controlled by a clock.
C.	Synchronous events do not need a clock to control them.
D.	Only asynchronous events need a control clock.
Answer» B. Asynchronous events are controlled by a clock.

Discussion

335.	A principle regarding most display decoders is that when the correct input is present, the related output will switch:
A.	HIGH
B.	to high impedance
C.	to an open
D.	LOW
Answer» E.

Discussion

336.	A modulus-10 counter must have ________.
A.	10 flip-flops
B.	flip-flops
C.	2 flip-flops
D.	synchronous clocking
Answer» C. 2 flip-flops

Discussion

337.	What type of device is shown below?
A.	4-bit bidirectional universal shift register
B.	Parallel in/parallel out shift register with bidirectional data flow
C.	2-way parallel in/serial out bidirectional register
D.	2-bit serial in/4-bit parallel out bidirectional shift register
Answer» B. Parallel in/parallel out shift register with bidirectional data flow

Discussion

338.	What does the triangle on the clock input of a J-K flip-flop mean?
A.	level enabled
B.	edge-triggered
Answer» C.

Discussion

339.	A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
A.	constantly LOW
B.	constantly HIGH
C.	a 20 kHz square wave
D.	a 10 kHz square wave
Answer» E.

Discussion

340.	The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
A.	opposite, active clock edge
B.	inverted, positive clock edge
C.	quiescent, negative clock edge
D.	reset, synchronous clock edge
Answer» B. inverted, positive clock edge

Discussion

341.	Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
A.	True
B.	False
Answer» C.

Discussion

342.	A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
A.	clock is LOW
B.	slave is transferring
C.	flip-flop is reset
D.	clock is HIGH
Answer» E.

Discussion

343.	How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
A.	It can't be done.
B.	Invert the Q outputs.
C.	Invert the
D.	<i>S-R</i>
E.	inputs.
Answer» D. <i>S-R</i>

Discussion

344.	What is the difference between the enable input of the 7475 and the clock input of the 7474?
A.	The 7475 is edge-triggered.
B.	The 7474 is edge-triggered.
Answer» C.

Discussion

345.	The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
A.	parity error checking
B.	ones catching
C.	digital discrimination
D.	digital filtering
Answer» C. digital discrimination

Discussion

346.	What is another name for a one-shot?
A.	Monostable
B.	Multivibrator
C.	Bistable
D.	Astable
Answer» B. Multivibrator

Discussion

347.	On a master-slave flip-flop, when is the master enabled?
A.	when the gate is LOW
B.	when the gate is HIGH
C.	both of the above
D.	neither of the above
Answer» C. both of the above

Discussion

348.	A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.
A.	10 kHz
B.	20 kHz
C.	30 kHz
D.	60 kHz
Answer» D. 60 kHz

Discussion

349.	A multiplexed display being driven by a logic circuit:
A.	accepts data inputs from one line and passes this data to multiple output lines
B.	accepts data inputs from several lines and allows one of them at a time to pass to the output
C.	accepts data inputs from multiple lines and passes this data to multiple output lines
D.	accepts data inputs from several lines and multiplexes this input data to four BCD lines
Answer» C. accepts data inputs from multiple lines and passes this data to multiple output lines

Discussion

350.	What is meant by parallel load of a counter?
A.	Each FF is loaded with data on a separate clock.
B.	The counter is cleared.
C.	All FFs are preset with data.
Answer» D.

Discussion

Explore topic-wise MCQs in Engineering.

The problem of interfacing IC logic families that have different supply voltages (VCC's) can be solved by using a:

The term buffer/driver signifies the ability to provide low output currents to drive light loads.

Why is the operating frequency for CMOS devices critical for determining power dissipation?

The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of:

Which family of devices has the characteristic of preventing saturation during operation?

How many 74LSTTL logic gates can be driven from a 74TTL gate?

From the following specifications determine the fan-out for the logic family.

CLB is the acronym for ________.

What can the GAL22V10 do that the GAL16V8 cannot?

The output of this circuit is always ________.

By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible.

Now many times can a GAL be erased and reprogrammed?

Which of the following increases the number of product terms by borrowing unused product from other macrocells?

MPGA stands for:

Which of the figures shown below represents the exclusive-NOR gate?

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output?

Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be HIGH. What is the status of the Y output?

Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.

Which of the following is not generally associated with flip-flops?

What is one disadvantage of an S-R flip-flop?

Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

One example of the use of an S-R flip-flop is as a(n):

A J-K flip-flop is in a "no change" condition when ________.

What is the difference between the 7476 and the 74LS76?

Which is not an Altera primitive port identifier?

The timing network that sets the output frequency of a 555 astable circuit contains ________.

MOD-6 and MOD-12 counters and multiples are most commonly used as:

Which of the following is an invalid state in an 8421 BCD counter?

After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?

How many different states does a 2-bit asynchronous counter have?

Which of the following statements are true?

A principle regarding most display decoders is that when the correct input is present, the related output will switch:

A modulus-10 counter must have ________.

What type of device is shown below?

What does the triangle on the clock input of a J-K flip-flop mean?

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

What is the difference between the enable input of the 7475 and the clock input of the 7474?

The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.

What is another name for a one-shot?

On a master-slave flip-flop, when is the master enabled?

A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.

A multiplexed display being driven by a logic circuit:

What is meant by parallel load of a counter?

The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their state(s) at the .