2291 + Mcqs in Digital Electronics Page 10 McqOptions

451.	If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
A.	An invalid state will exist.
B.	No change will occur in the output.
C.	The output will toggle.
D.	The output will reset.
Answer» C. The output will toggle.

Discussion

452.	The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?
A.	There is no problem.
B.	The clock should be held HIGH.
C.	The PRE is stuck LOW.
D.	The CLR is stuck HIGH.
Answer» D. The CLR is stuck HIGH.

Discussion

453.	Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
A.	True
B.	False
Answer» C.

Discussion

454.	Which is not a real advantage of HDL?
A.	Using higher levels of abstraction
B.	Tailoring components to exactly fit the needs of the project
C.	The use of graphical tools
D.	Using higher levels of abstraction and tailoring components to exactly fit the needs of the project
Answer» D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

Discussion

455.	Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
A.	00
B.	11
C.	01
D.	10
Answer» B. 11

Discussion

456.	Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
A.	cross coupling
B.	gate impedance
C.	low input voltages
D.	asynchronous operation
Answer» B. gate impedance

Discussion

457.	Edge-triggered flip-flops must have:
A.	very fast response times.
B.	at least two inputs to handle rising and falling edges.
C.	a pulse transition detector.
D.	active-LOW inputs and complemented outputs.
Answer» D. active-LOW inputs and complemented outputs.

Discussion

458.	In VHDL, how is each instance of a component addressed?
A.	A name followed by a colon and the name of the library primitive
B.	A name followed by a semicolon and the component type
C.	A name followed by the library being used
D.	A name followed by the component library number
Answer» B. A name followed by a semicolon and the component type

Discussion

459.	The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):
A.	NOR gate
B.	OR gate
C.	AND gate
D.	NOT operation
Answer» C. AND gate

Discussion

460.	Which of the symbols shown below represents an AND gate?
A.	a
B.	b
C.	c
D.	d
Answer» E.

Discussion

461.	For a three-input AND gate, with the input waveforms as shown below, which output waveform is correct?
A.	a
B.	b
C.	c
D.	d
Answer» D. d

Discussion

462.	The special software application that translates from HDL into a grid of 1's and 0's, which can be loaded into a PLD, is called a:
A.	formatter.
B.	compiler.
C.	programmable wiring.
D.	CPU.
Answer» C. programmable wiring.

Discussion

463.	As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
A.	very long.
B.	very short.
C.	at a maximum value to enable the input control signals to stabilize.
D.	of no consequence as long as the levels are within the determinate range of value.
Answer» C. at a maximum value to enable the input control signals to stabilize.

Discussion

464.	A positive edge-triggered D flip-flop will store a 1 when ________.
A.	the D input is HIGH and the clock transitions from HIGH to LOW
B.	the D input is HIGH and the clock transitions from LOW to HIGH
C.	the D input is HIGH and the clock is LOW
D.	the D input is HIGH and the clock is HIGH
Answer» C. the D input is HIGH and the clock is LOW

Discussion

465.	If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
A.	No change will occur in the output.
B.	An invalid state will exist.
C.	The output will toggle.
D.	The output will reset.
Answer» B. An invalid state will exist.

Discussion

466.	Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.
A.	1 kHz
B.	2 kHz
C.	4 kHz
D.	16 kHz
Answer» C. 4 kHz

Discussion

467.	A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
A.	The power supply is probably noisy.
B.	The switch contacts are bouncing.
C.	The socket contacts on the register IC are corroded.
D.	The register IC is intermittent and failure is imminent.
Answer» C. The socket contacts on the register IC are corroded.

Discussion

468.	The output of a gated S-R flip-flop changes only if the:
A.	flip-flop is set
B.	control input data has changed
C.	flip-flop is reset
D.	input data has no change
Answer» C. flip-flop is reset

Discussion

469.	Simplify the expression using DeMorgan's theorems.
A.	<img src="/_files/images/digital-electronics/digital-systems/mca3_1019a1.gif">
B.	<img src="/_files/images/digital-electronics/digital-systems/mca3_1019b1.gif">
C.	<img src="/_files/images/digital-electronics/digital-systems/mca3_1019c1.gif">
D.	<img src="/_files/images/digital-electronics/digital-systems/mca3_1019d1.gif">
Answer» C. <img src="/_files/images/digital-electronics/digital-systems/mca3_1019c1.gif">

Discussion

470.	To completely load and then unload an 8-bit register requires how many clock pulses?
A.	2
B.	4
C.	8
D.	16
Answer» E.

Discussion

471.	What is one disadvantage of an S-R flip-flop?
A.	It has no enable input.
B.	It has an invalid state.
C.	It has no clock input.
D.	It has only a single output.
Answer» C. It has no clock input.

Discussion

472.	Which of the following best describes the action of pulse-triggered FF's?
A.	The clock and the S-R inputs must be pulse shaped.
B.	The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
C.	A pulse on the clock transfers data from input to output.
D.	The synchronous inputs must be pulsed.
Answer» C. A pulse on the clock transfers data from input to output.

Discussion

473.	An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.
A.	HIGHs are applied simultaneously to both inputs S and R
B.	LOWs are applied simultaneously to both inputs S and R
C.	a LOW is applied to the S input while a HIGH is applied to the R input
D.	a HIGH is applied to the S input while a LOW is applied to the R input
Answer» B. LOWs are applied simultaneously to both inputs S and R

Discussion

474.	For a three-input NOR gate, with the input waveforms as shown below, which output waveform is correct?
A.	a
B.	b
C.	c
D.	d
Answer» B. b

Discussion

475.	What is the indication of a short to ground in the output of a driving gate?
A.	Only the output of the defective gate is affected.
B.	There is a signal loss to all load gates.
C.	The node may be stuck in either the HIGH or the LOW state.
D.	The affected node will be stuck in the HIGH state.
Answer» C. The node may be stuck in either the HIGH or the LOW state.

Discussion

476.	What will a design engineer do after he/she is satisfied that the design will work?
A.	Put it in a flow chart
B.	Program a chip and test it
C.	Give the design to a technician to verify the design
D.	Perform a vector test
Answer» C. Give the design to a technician to verify the design

Discussion

477.	In VHDL, macrofunctions is/are:
A.	digital circuits.
B.	analog circuits.
C.	a set of bit vectors.
D.	preprogrammed TTL devices.
Answer» E.

Discussion

478.	Which of the following is an important feature of the sum-of-products form of expressions?
A.	All logic circuits are reduced to nothing more than simple AND and OR operations.
B.	The delay times are greatly reduced over other forms.
C.	No signal must pass through more than two gates, not including inverters.
D.	The maximum number of gates that any signal must pass through is reduced by a factor of two.
Answer» B. The delay times are greatly reduced over other forms.

Discussion

479.	An output gate is connected to four input gates; the circuit does not function. Preliminary tests with the DMM indicate that the power is applied; scope tests show that the primary input gate has a pulsing signal, while the interconnecting node has no signal. The four load gates are all on different ICs. Which instrument will best help isolate the problem?
A.	Current tracer
B.	Logic probe
C.	Oscilloscope
D.	Logic analyzer
Answer» B. Logic probe

Discussion

480.	What is the indication of a short on the input of a load gate?
A.	Only the output of the defective gate is affected.
B.	There is a signal loss to all gates on the node.
C.	The affected node will be stuck in the LOW state.
D.	There is a signal loss to all gates on the node, and the affected node will be stuck in the LOW state.
Answer» E.

Discussion

481.	In HDL, LITERALS is/are:
A.	digital systems.
B.	scalars.
C.	binary coded decimals.
D.	a numbering system.
Answer» C. binary coded decimals.

Discussion

482.	Which of the K-maps given below represents the expression X = AC + BC + B?
A.	a
B.	b
C.	c
D.	d
Answer» D. d

Discussion

483.	A decoder can be used as a demultiplexer by ________.
A.	tying all enable pins LOW
B.	tying all data-select lines LOW
C.	tying all data-select lines HIGH
D.	using the input lines for data selection and an enable line for data input
Answer» E.

Discussion

484.	How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010?
A.	1
B.	2
C.	3
D.	4
Answer» D. 4

Discussion

485.	Which statement below best describes a Karnaugh map?
A.	A Karnaugh map can be used to replace Boolean rules.
B.	The Karnaugh map eliminates the need for using NAND and NOR gates.
C.	Variable complements can be eliminated by using Karnaugh maps.
D.	Karnaugh maps provide a visual approach to simplifying Boolean expressions.
Answer» E.

Discussion

486.	Each "1" entry in a K-map square represents:
A.	a HIGH for each input truth table condition that produces a HIGH output.
B.	a HIGH output on the truth table for all LOW input combinations.
C.	a LOW output for all possible HIGH input conditions.
D.	a DON'T CARE condition for all possible input truth table combinations.
Answer» B. a HIGH output on the truth table for all LOW input combinations.

Discussion

487.	For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?
A.	a
B.	b
C.	c
D.	d
Answer» E.

Discussion

488.	A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001?
A.	0
B.	3
C.	9
D.	None. All outputs are HIGH.
Answer» D. None. All outputs are HIGH.

Discussion

489.	What type of logic circuit is represented by the figure shown below?
A.	XOR
B.	XNOR
C.	XAND
D.	XNAND
Answer» C. XAND

Discussion

490.	What is the difference between an astable multivibrator and a monostable multivibrator?
A.	The astable is free running.
B.	The astable needs to be clocked.
C.	The monostable is free running.
D.	none of the above
Answer» B. The astable needs to be clocked.

Discussion

491.	Is there any limit to the number of times that a 74123 can be retriggered?
A.	yes
B.	no
Answer» C.

Discussion

492.	The Ex-NOR is sometimes called the ________.
A.	parity gate
B.	equality gate
C.	inverted OR
D.	parity gate or the equality gate
Answer» C. inverted OR

Discussion

493.	Parity systems are defined as either________ or ________ and will add an extra ________ to the digital information being transmitted.
A.	positive, negative, byte
B.	odd, even, bit
C.	upper, lower, digit
D.	on, off, decimal
Answer» C. upper, lower, digit

Discussion

494.	Which type of gate can be used to add two bits?
A.	Ex-OR
B.	Ex-NOR
C.	Ex-NAND
D.	NOR
Answer» B. Ex-NOR

Discussion

495.	Why is an exclusive-NOR gate also called an equality gate?
A.	The output is false if the inputs are equal.
B.	The output is true if the inputs are opposite.
C.	The output is true if the inputs are equal.
Answer» D.

Discussion

496.	Pulse stretching, time-delay, and pulse generation are all easily accomplished with which type of multivibrator circuit?
A.	astable
B.	monostable
C.	multistable
D.	bistable
Answer» C. multistable

Discussion

497.	The internal circuitry of the 555 timer consists of ________, an R-S flip-flop, a transistor switch, an output buffer amplifier, and a voltage divider.
A.	a comparator
B.	a voltage amplifier
C.	two comparators
D.	a peak detector
Answer» D. a peak detector

Discussion

498.	With most monostable multivibrators, what is the Q output when no input trigger has occurred?
A.	LOW
B.	+5 V
C.	SET
D.	HIGH
Answer» B. +5 V

Discussion

499.	The output of the astable circuit ________.
A.	constantly switches between two states
B.	is LOW until a trigger is received
C.	is HIGH until a trigger is received
D.	floats until triggered
Answer» B. is LOW until a trigger is received

Discussion

500.	If a diode is connected across resistor RB (positive end up) in the given figure, what is the new duty cycle of the output waveform?
A.	56%
B.	44%
C.	21.6%
D.	17.4%
Answer» D. 17.4%

Discussion

Explore topic-wise MCQs in Engineering.

If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.

Which is not a real advantage of HDL?

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

Edge-triggered flip-flops must have:

In VHDL, how is each instance of a component addressed?

The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):

Which of the symbols shown below represents an AND gate?

For a three-input AND gate, with the input waveforms as shown below, which output waveform is correct?

The special software application that translates from HDL into a grid of 1's and 0's, which can be loaded into a PLD, is called a:

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

A positive edge-triggered D flip-flop will store a 1 when ________.

If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.

A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

The output of a gated S-R flip-flop changes only if the:

Simplify the expression using DeMorgan's theorems.

To completely load and then unload an 8-bit register requires how many clock pulses?

What is one disadvantage of an S-R flip-flop?

Which of the following best describes the action of pulse-triggered FF's?

An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.

For a three-input NOR gate, with the input waveforms as shown below, which output waveform is correct?

What is the indication of a short to ground in the output of a driving gate?

What will a design engineer do after he/she is satisfied that the design will work?

In VHDL, macrofunctions is/are:

Which of the following is an important feature of the sum-of-products form of expressions?

What is the indication of a short on the input of a load gate?

In HDL, LITERALS is/are:

Which of the K-maps given below represents the expression X = AC + BC + B?

A decoder can be used as a demultiplexer by ________.

How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010?

Which statement below best describes a Karnaugh map?

Each "1" entry in a K-map square represents:

For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?

A certain BCD-to-decimal decoder has active-HIGH inputs and active-LOW outputs. Which output goes LOW when the inputs are 1001?

What type of logic circuit is represented by the figure shown below?

What is the difference between an astable multivibrator and a monostable multivibrator?

Is there any limit to the number of times that a 74123 can be retriggered?

The Ex-NOR is sometimes called the ________.

Parity systems are defined as either________ or ________ and will add an extra ________ to the digital information being transmitted.

Which type of gate can be used to add two bits?

Why is an exclusive-NOR gate also called an equality gate?

Pulse stretching, time-delay, and pulse generation are all easily accomplished with which type of multivibrator circuit?

The internal circuitry of the 555 timer consists of ________, an R-S flip-flop, a transistor switch, an output buffer amplifier, and a voltage divider.

With most monostable multivibrators, what is the Q output when no input trigger has occurred?

The output of the astable circuit ________.

If a diode is connected across resistor RB (positive end up) in the given figure, what is the new duty cycle of the output waveform?

Parity systems are defined as either or and will add an extra to the digital information being transmitted.