MCQOPTIONS
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MCQOPTIONS
This section includes 187 Mcqs, each offering curated multiple-choice questions to sharpen your Electrical Engineering knowledge and support exam preparation. Choose a topic below to get started.
| 151. |
How many shift registers are used in a 4 bit serial adder? |
| A. | 4 |
| B. | 3 |
| C. | 2 |
| D. | 5 |
| Answer» D. 5 | |
| 152. |
What are carry generate combinations? |
| A. | if all the input are same then a carry is generated |
| B. | if all of the output are independent of the inputs |
| C. | if all of the input are dependent on the output |
| D. | if all of the output are dependent on the input |
| Answer» C. if all of the input are dependent on the output | |
| 153. |
The inverter can be produced with how many NAND gates? |
| A. | 2 |
| B. | 1 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 154. |
The selector inputs to an arithmetic/logic unit (ALU) determine the |
| A. | selection of the ic |
| B. | arithmetic or logic function |
| C. | data word selection |
| D. | clock frequency to be used |
| Answer» C. data word selection | |
| 155. |
Which of the following is correct for full adders? |
| A. | full adders have the capability of directly adding decimal numbers |
| B. | full adders are used to make half adders |
| C. | full adders are limited to two inputs since there are only two binary digits |
| D. | in a parallel full adder, the first stage may be a half adder |
| Answer» E. | |
| 156. |
When performing subtraction by addition in the 2’s-complement system |
| A. | the minuend and the subtrahend are both changed to the 2’s-complement |
| B. | the minuend is changed to 2’s- complement and the subtrahend is left in its original form |
| C. | the minuend is left in its original form and the subtrahend is changed to its 2’s- complement |
| D. | the minuend and subtrahend are both left in their original form |
| Answer» D. the minuend and subtrahend are both left in their original form | |
| 157. |
How many basic binary subtraction operations are possible? |
| A. | 1 |
| B. | 4 |
| C. | 3 |
| D. | 2 |
| Answer» C. 3 | |
| 158. |
The binary subtraction of 0 – 0 = ? |
| A. | difference = 0, borrow = 0 |
| B. | difference = 1, borrow = 0 |
| C. | difference = 1, borrow = 1 |
| D. | difference = 0, borrow = 1 |
| Answer» B. difference = 1, borrow = 0 | |
| 159. |
What is the major difference between half- adders and full-adders? |
| A. | full-adders are made up of two half-adders |
| B. | full adders can handle double-digit numbers |
| C. | full adders have a carry input capability |
| D. | half adders can handle only single-digit numbers |
| Answer» D. half adders can handle only single-digit numbers | |
| 160. |
What is the first thing you will need if you are going to use a macro-function? |
| A. | a complicated design project |
| B. | an experienced design engineer |
| C. | good documentation |
| D. | experience in hdl |
| Answer» E. | |
| 161. |
Controlled buffers can be useful |
| A. | to control the circuit’s output into the bus |
| B. | in comparison of component’s output with its input |
| C. | in increasing the output from its low input |
| D. | all of the mentioned |
| Answer» B. in comparison of component’s output with its input | |
| 162. |
Why XOR gate is called an inverter? |
| A. | because of the same input |
| B. | because of the same output |
| C. | it behaves like a not gate |
| D. | it behaves like a and gate |
| Answer» D. it behaves like a and gate | |
| 163. |
A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is |
| A. | ex-nor gate |
| B. | or gate |
| C. | ex-or gate |
| D. | nand gate |
| Answer» B. or gate | |
| 164. |
How many AND, OR and EXOR gates are required for the configuration of full |
| A. | 1, 2, 2 |
| B. | 2, 1, 2 |
| C. | 3, 1, 2 |
| D. | 4, 0, 1 |
| Answer» C. 3, 1, 2 | |
| 165. |
There are              cells in a 4-variable K- map. |
| A. | 12 |
| B. | 16 |
| C. | 18 |
| D. | 8 |
| Answer» C. 18 | |
| 166. |
                           expressions can be implemented using either (1) 2-level AND- OR logic circuits or (2) 2-level NAND logic circuits. |
| A. | pos |
| B. | literals |
| C. | sop |
| D. | pos |
| Answer» D. pos | |
| 167. |
The expression Y=(A+B)(B+C)(C+A) shows the                    operation. |
| A. | and |
| B. | pos |
| C. | sop |
| D. | nand |
| Answer» C. sop | |
| 168. |
Which of the following correctly describes the distributive law. |
| A. | ( a+b)(c+d)=ab+cd |
| B. | (a+b).c=ac+bc |
| C. | (ab)(a+b)=ab |
| D. | (a.b)c=ac.ab |
| Answer» C. (ab)(a+b)=ab | |
| 169. |
The expression of a NAND gate is |
| A. | a.b |
| B. | a’b+ab’ |
| C. | (a.b)’ |
| D. | (a+b)’ |
| Answer» D. (a+b)’ | |
| 170. |
The                  gate is an OR gate followed by a NOT gate. |
| A. | nand |
| B. | exor |
| C. | nor |
| D. | exnor |
| Answer» D. exnor | |
| 171. |
Number of outputs in a half adder |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| Answer» C. 3 | |
| 172. |
How many AND gates are required to realize the following expression Y=AB+BC? |
| A. | 4 |
| B. | 8 |
| C. | 1 |
| D. | 2 |
| Answer» E. | |
| 173. |
The complement of the input given is obtained in case of: |
| A. | nor |
| B. | and+nor |
| C. | not |
| D. | ex-or |
| Answer» D. ex-or | |
| 174. |
There are 5 universal gates. |
| A. | true |
| B. | false |
| Answer» C. | |
| 175. |
A Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â is a circuit with only one output but can have multiple inputs. |
| A. | logic gate |
| B. | truth table |
| C. | binary circuit |
| D. | boolean circuit |
| Answer» B. truth table | |
| 176. |
The Output is LOW if any one of the inputs is HIGH in case of a                    gate. |
| A. | nor |
| B. | nand |
| C. | or |
| D. | and |
| Answer» C. or | |
| 177. |
Complement of the expression A’B + CD’ is |
| A. | (a’ + b)(c’ + d) |
| B. | (a + b’)(c’ + d) |
| C. | (a’ + b)(c’ + d) |
| D. | (a + b’)(c + d’) |
| Answer» C. (a’ + b)(c’ + d) | |
| 178. |
On subtracting +28 from +29 using 2’s complement, we get |
| A. | 11111010 |
| B. | 111111001 |
| C. | 100001 |
| D. | 1 |
| Answer» E. | |
| 179. |
On addition of -46 and +28 using 2’s complement, we get |
| A. | 00101110 |
| B. | 0101110 |
| C. | 00101111 |
| D. | 1001111 |
| Answer» C. 00101111 | |
| 180. |
On addition of +38 and -20 using 2’s complement, we get |
| A. | 11110001 |
| B. | 100001110 |
| C. | 010010 |
| D. | 110101011 |
| Answer» D. 110101011 | |
| 181. |
1011)2 = (11.6875)10 |
| A. | (111101)2 |
| B. | (010100)2 |
| C. | (111100)2 |
| D. | (101010)2 |
| Answer» C. (111100)2 | |
| 182. |
Convert the binary number (01011.1011)2 into decimal: |
| A. | (11.6875)10 |
| B. | (11.5874)10 |
| C. | (10.9876)10 |
| D. | (10.7893)10 |
| Answer» B. (11.5874)10 | |
| 183. |
(170)10 is equivalent to |
| A. | (fd)16 |
| B. | (df)16 |
| C. | (aa)16 |
| D. | (af)16 |
| Answer» D. (af)16 | |
| 184. |
The octal equivalent of the decimal number (417)10 is |
| A. | (641)8 |
| B. | (619)8 |
| C. | (640)8 |
| D. | (598)8 |
| Answer» B. (619)8 | |
| 185. |
The octal number (651.124)8 is equivalent to |
| A. | 16 |
| B. | (1b0.10)16 |
| C. | (1a8.a3)16 |
| D. | (1b0.b0)16 |
| Answer» B. (1b0.10)16 | |
| 186. |
Convert the hexadecimal number (1E2)16 to decimal: |
| A. | 480 |
| B. | 483 |
| C. | 482 |
| D. | 484 |
| Answer» D. 484 | |
| 187. |
The given hexadecimal number (1E.53)16 is equivalent to |
| A. | (35.684)8 |
| B. | (36.246)8 |
| C. | (34.340)8 |
| D. | (35.599)8 |
| Answer» C. (34.340)8 | |