MCQOPTIONS
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MCQOPTIONS
This section includes 20 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The characteristic equation of D-flip-flop implies that ___________ |
| A. | The next state is dependent on previous state |
| B. | The next state is dependent on present state |
| C. | The next state is independent of previous state |
| D. | The next state is independent of present state |
| Answer» E. | |
| 2. |
Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’? |
| A. | Due to its capability to receive data from flip-flop |
| B. | Due to its capability to store data in flip-flop |
| C. | Due to its capability to transfer the data into flip-flop |
| D. | Due to erasing the data from the flip-flop |
| Answer» D. Due to erasing the data from the flip-flop | |
| 3. |
A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states? |
| A. | CLK = NGT, D = 0 |
| B. | CLK = PGT, D = 0 |
| C. | CLOCK NGT, D = 1 |
| D. | CLOCK PGT, D = 1 |
| Answer» E. | |
| 4. |
With regard to a D latch ________ |
| A. | The Q output follows the D input when EN is LOW |
| B. | The Q output is opposite the D input when EN is LOW |
| C. | The Q output follows the D input when EN is HIGH |
| D. | The Q output is HIGH regardless of EN’s input state |
| Answer» D. The Q output is HIGH regardless of EN’s input state | |
| 5. |
Which statement describes the BEST operation of a negative-edge-triggered D flip-flop? |
| A. | The logic level at the D input is transferred to Q on NGT of CLK |
| B. | The Q output is ALWAYS identical to the CLK input if the D input is HIGH |
| C. | The Q output is ALWAYS identical to the D input when CLK = PGT |
| D. | The Q output is ALWAYS identical to the D input |
| Answer» B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH | |
| 6. |
In D flip-flop, if clock input is HIGH & D=1, then output is ___________ |
| A. | 0 |
| B. | 1 |
| C. | Forbidden |
| D. | Toggle |
| Answer» B. 1 | |
| 7. |
In D flip-flop, if clock input is LOW, the D input ___________ |
| A. | Has no effect |
| B. | Goes high |
| C. | Goes low |
| D. | Has effect |
| Answer» B. Goes high | |
| 8. |
In D flip-flop, D stands for _____________ |
| A. | Distant |
| B. | Data |
| C. | Desired |
| D. | Delay |
| Answer» C. Desired | |
| 9. |
WITH_REGARD_TO_A_D_LATCH,_________?$ |
| A. | The Q output follows the D input when EN is LOW |
| B. | The Q output is opposite the D input when EN is LOW |
| C. | The Q output follows the D input when EN is HIGH |
| D. | The Q output is HIGH regardless of EN’s input state |
| Answer» D. The Q output is HIGH regardless of EN‚Äö√Ñ√∂‚àö√ë‚àö¬•s input state | |
| 10. |
Which of the following describes the operation of a positive edge-triggered D flip-flop?$ |
| A. | If both inputs are HIGH, the output will toggle |
| B. | The output will follow the input on the leading edge of the clock |
| C. | When both inputs are LOW, an invalid state exists |
| D. | The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock |
| Answer» C. When both inputs are LOW, an invalid state exists | |
| 11. |
Which of the following is correct for a D latch?$ |
| A. | The output toggles if one of the inputs is held HIGH |
| B. | Q output follows the input D when the enable is HIGH |
| C. | Only one of the inputs can be HIGH at a time |
| D. | The output complement follows the input when enabled |
| Answer» C. Only one of the inputs can be HIGH at a time | |
| 12. |
The characteristic equation of D-flip-flop implies that |
| A. | The next state is dependent on previous state |
| B. | The next state is dependent on present state |
| C. | The next state is independent of previous state |
| D. | The next state is independent of present state |
| Answer» E. | |
| 13. |
Why do the D flip-flops receives its designation or nomenclature as ‘Data Flip-flops’?$ |
| A. | Due to its capability to receive data from flip-flop |
| B. | Due to its capability to store data in flip-flop |
| C. | Due to its capability to transfer the data into flip-flop |
| D. | All of the Mentioned |
| Answer» D. All of the Mentioned | |
| 14. |
A positive edge-triggered D flip-flop will store a 1 when ________ |
| A. | The D input is HIGH and the clock transitions from HIGH to LOW |
| B. | The D input is HIGH and the clock transitions from LOW to HIGH |
| C. | The D input is HIGH and the clock is LOW |
| D. | The D input is HIGH and the clock is HIGH |
| Answer» C. The D input is HIGH and the clock is LOW | |
| 15. |
In D flip-flop, if clock input is HIGH & D=1, then output is |
| A. | 0 |
| B. | 1 |
| C. | Forbidden |
| D. | Toggle |
| Answer» B. 1 | |
| 16. |
In D flip-flop, if clock input is LOW, the D input |
| A. | Goes high |
| B. | Has no effect |
| C. | Goes low |
| D. | None of the Mentioned |
| Answer» B. Has no effect | |
| 17. |
A D flip-flop can be constructed from an ______ flip-flop. |
| A. | S-R |
| B. | J-K |
| C. | T |
| D. | None of the Mentioned |
| Answer» B. J-K | |
| 18. |
The D flip-flop has ______ output/outputs. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | None of the Mentioned |
| Answer» B. 3 | |
| 19. |
The D flip-flop has _______ input. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 20. |
In D flip-flop, D stands for |
| A. | Distant |
| B. | Delay |
| C. | Desired |
| D. | None of the Mentioned |
| Answer» C. Desired | |