MCQOPTIONS
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This section includes 14 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Fault coverage is ______ in finite state machines. |
| A. | less |
| B. | more |
| C. | equal |
| D. | none of the mentioned |
| Answer» C. equal | |
| 2. |
Finite state machine will initially set to all zeroes. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 3. |
_______ is used to control the read and write operations. |
| A. | active low synchronous reset |
| B. | active high synchronous reset |
| C. | active low synchronous preset |
| D. | active high synchronous preset |
| Answer» C. active low synchronous preset | |
| 4. |
Address ordering minimizes the logic of finite state machines. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 5. |
FAULT_COVERAGE_IS________IN_FINITE_STATE_MACHINES?$ |
| A. | less |
| B. | more |
| Answer» C. | |
| 6. |
Finite state machine will initially set to all zeroes? |
| A. | true |
| B. | false |
| Answer» B. false | |
| 7. |
_______ is used to control the read and write operations |
| A. | active low synchronous reset |
| B. | active high synchronous reset |
| C. | active low synchronous preset |
| D. | active high synchronous preset |
| Answer» C. active low synchronous preset | |
| 8. |
In finite state machine the data in and data out are |
| A. | in same ports |
| B. | different ports |
| C. | same register |
| D. | different register |
| Answer» C. same register | |
| 9. |
Address ordering minimizes the logic of finite state machine. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 10. |
Finite state machines are used for |
| A. | deterministic test patterns |
| B. | algorithmic test patterns |
| C. | random test patterns |
| D. | pseudo random test patterns |
| Answer» C. random test patterns | |
| 11. |
The least significant bit toggles for |
| A. | every clock cycle |
| B. | every alternate clock cycle |
| C. | every two clock cycles |
| D. | every four clock cycles |
| Answer» B. every alternate clock cycle | |
| 12. |
The desired N value for counters is |
| A. | less than 50 |
| B. | less than 10 |
| C. | less than 25 |
| D. | less than 70 |
| Answer» D. less than 70 | |
| 13. |
How many test patterns are required to test the circuit using counters? |
| A. | 2<sup>n</sup> |
| B. | 2<sup>(n-1) </sup> |
| C. | 2<sup>n</sup> -1 |
| D. | 2<sup>n</sup> +1 |
| Answer» B. 2<sup>(n-1) </sup> | |
| 14. |
Counters detect only bridging faults. |
| A. | true |
| B. | false |
| Answer» C. | |