MCQOPTIONS
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MCQOPTIONS
This section includes 14 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Which of the following parameters are found using load capacitance? |
| A. | Delay time |
| B. | Power consumption |
| C. | Speed of the CMOS logic |
| D. | All of the mentioned |
| Answer» E. | |
| 2. |
Interconnect capacitance is formed due to ___________ |
| A. | Junction capacitance between gate and substrate |
| B. | Wire connecting the gates of 2 different inverters |
| C. | Parasitic capacitance existing between metal and polysilicon connection between 2 inverters |
| D. | All of the mentioned |
| Answer» D. All of the mentioned | |
| 3. |
Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in cascade configuration. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 4. |
The load capacitance is equivalent to ___________ |
| A. | Sum of all lumped linear capacitances between input and output node |
| B. | Sum of all junction capacitance between Vcc and ground |
| C. | Sum of all junction capacitance between input and output |
| D. | Sum of all lumped linear capacitances between output node and ground |
| Answer» B. Sum of all junction capacitance between Vcc and ground | |
| 5. |
The load capacitance is measured between ___________ |
| A. | Output node and input node |
| B. | Output node and Vcc |
| C. | Output node and ground |
| D. | Input node and ground |
| Answer» D. Input node and ground | |
| 6. |
When MOSFET is operating in saturation region, the gate to source capacitance is? |
| A. | 1/2*Cox*W*L |
| B. | 2/3*Cox*W*L |
| C. | Cox*W*L |
| D. | 1/3*Cox*W*L |
| Answer» C. Cox*W*L | |
| 7. |
In saturation mode operation, gate to drain capacitance is zero due to ___________ |
| A. | Gate and drain are interconnected |
| B. | Channel length is reduced |
| C. | Inversion layer doesn t exist |
| D. | Drain is connected to ground |
| Answer» C. Inversion layer doesn t exist | |
| 8. |
In linear mode operation, the parasitic capacitances that exists are ___________ |
| A. | Nonzero Gate to source capacitance |
| B. | Nonzero Gate to drain capacitance |
| C. | Zero gate to substrate capacitance |
| D. | All of the mentioned |
| Answer» E. | |
| 9. |
In cut-off mode, the value of gate to substrate capacitance is equal to ___________ |
| A. | Cox .(W- L) |
| B. | Cox W/ L |
| C. | Cox* W*L |
| D. | 0 |
| Answer» D. 0 | |
| 10. |
In Cut-off Mode, the capacitance Cgs will be equal to ___________ |
| A. | 2Cgd |
| B. | 0 |
| C. | Cgb |
| D. | All of the mentioned |
| Answer» C. Cgb | |
| 11. |
The capacitance that exist between Gate and Bulk is called as ___________ |
| A. | Oxide parasitic capacitance |
| B. | Metal oxide capacitance |
| C. | MOS capacitance |
| D. | None of the mentioned |
| Answer» B. Metal oxide capacitance | |
| 12. |
The proper DC model of MOSFET with capacitances is? |
| A. | <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3a.png"><img alt="The proper DC model of MOSFET with capacitances - option a" class="alignnone size-full wp-image-161941" height="312" sizes="(max-width: 372px) 100vw, 372px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3a.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3a.png 372w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3a-300x252.png 300w" width="372"/></a> |
| B. | <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3b.png"><img alt="The proper DC model of MOSFET with capacitances - option b" class="alignnone size-full wp-image-161943" height="312" sizes="(max-width: 372px) 100vw, 372px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3b.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3b.png 372w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3b-300x252.png 300w" width="372"/></a> |
| C. | <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3c.png"><img alt="The proper DC model of MOSFET with capacitances - option c" class="alignnone size-full wp-image-161944" height="312" sizes="(max-width: 372px) 100vw, 372px" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3c.png" srcset="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3c.png 372w, https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-load-wiring-capacitance-q3c-300x252.png 300w" width="372"/></a> |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 13. |
The parasitic capacitances found in MOSFET are ___________ |
| A. | Oxide related capacitances |
| B. | Inter electrode capacitance |
| C. | Electrolytic capacitance |
| D. | All of the mentioned |
| Answer» B. Inter electrode capacitance | |
| 14. |
The capacitances in MOSFET occurs due to _____________ |
| A. | Interconnects |
| B. | Difference in Doping concentration |
| C. | Difference in dopant materials |
| D. | All of the mentioned |
| Answer» E. | |