MCQOPTIONS
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MCQOPTIONS
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
THE_EXTRA_TIME_NEEDED_TO_BRING_THE_DATA_INTO_MEMORY_IN_CASE_OF_A_MISS_IS_CALLED_AS______?$ |
| A. | Delay |
| B. | Propagation time |
| C. | Miss penalty |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 2. |
The_miss_penalty_can_be_reduced_by_improving_the_mechanisms_for_data_transfer_between_the_different_levels_of_hierarchy.$ |
| A. | True |
| B. | False |
| Answer» B. False | |
| 3. |
If hit rates are well below 0.9, then they’re called as speedy computers?# |
| A. | True |
| B. | False |
| Answer» C. | |
| 4. |
In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of ______$ |
| A. | Hit |
| B. | Miss |
| C. | Delay |
| D. | None of the mentioned |
| Answer» B. Miss | |
| 5. |
In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when _____ occurs.$ |
| A. | Delay |
| B. | Miss |
| C. | Hit |
| D. | Delayed hit |
| Answer» C. Hit | |
| 6. |
The number failed attempts to access memory, stated in the form of a fraction is called as _________ |
| A. | Hit rate |
| B. | Miss rate |
| C. | Failure rate |
| D. | Delay rate |
| Answer» C. Failure rate | |
| 7. |
The number successful accesses to memory stated as a fraction is called as _____ |
| A. | Hit rate |
| B. | Miss rate |
| C. | Success rate |
| D. | Access rate |
| Answer» B. Miss rate | |
| 8. |
In memory interleaving, the lower order bits of the address is used to |
| A. | Get the data |
| B. | Get the address of the module |
| C. | Get the address of the data within the module |
| D. | None of the mentioned |
| Answer» C. Get the address of the data within the module | |
| 9. |
When consecutive memory locations are accessed only one module is accessed at a time. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 10. |
The main memory is structured into modules each with its own address register called ______ |
| A. | ABR |
| B. | TLB |
| C. | PC |
| D. | IR |
| Answer» B. TLB | |