MCQOPTIONS
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MCQOPTIONS
This section includes 585 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 401. |
Once the BUS is granted to a device ___ |
| A. | It activates the BUS busy line |
| B. | Performs the required operation |
| C. | Raises an interrupt |
| D. | All of the mentioned |
| Answer» B. Performs the required operation | |
| 402. |
When the processor recieves the request from a device, it responds by sending __ |
| A. | Acknowledge signal |
| B. | BUS grant signal |
| C. | Response signal |
| D. | None of the mentioned |
| Answer» C. Response signal | |
| 403. |
The circuit used for the request line is a ____ |
| A. | Open-collector |
| B. | EX-OR circuit |
| C. | Open-drain |
| D. | Nand circuit |
| Answer» D. Nand circuit | |
| 404. |
____ BUS arbitration appproach uses the involvement of the processor |
| A. | Centralised arbitration |
| B. | Distributed arbitration |
| C. | Random arbitration |
| D. | All of the mentioned |
| Answer» B. Distributed arbitration | |
| 405. |
The DMA transfer is initiated by ____ |
| A. | Processor |
| B. | The process being executed |
| C. | I/O devices |
| D. | OS |
| Answer» D. OS | |
| 406. |
The device which is allowed to initiate data transfers on the BUS at any time is called ____ |
| A. | BUS master |
| B. | Processor |
| C. | BUS arbitrator |
| D. | Controller |
| Answer» B. Processor | |
| 407. |
To resolve the clash over the access of the system BUS we use __ |
| A. | Multiple BUS |
| B. | BUS arbitrator |
| C. | Priority access |
| D. | None of the mentioned |
| Answer» C. Priority access | |
| 408. |
The registers of the controller are _ |
| A. | 64 bits |
| B. | 24 bits |
| C. | 32 bits |
| D. | 16 bits |
| Answer» D. 16 bits | |
| 409. |
When process requests for a DMA transfer |
| A. | Then the process is temporarily suspended |
| B. | The process continues execution |
| C. | Another process gets executed |
| D. | process is temporarily suspended & Another process gets executed |
| Answer» E. | |
| 410. |
To overcome the conflict over the possession of the BUS we use ___ |
| A. | Optimizers |
| B. | BUS arbitrators |
| C. | Multiple BUS structure |
| D. | None of the mentioned |
| Answer» C. Multiple BUS structure | |
| 411. |
The techinique whereby the DMA controller steals the access cycles of the processor to operate is called |
| A. | Fast conning |
| B. | Memory Con |
| C. | Cycle stealing |
| D. | Memory stealing |
| Answer» D. Memory stealing | |
| 412. |
The controller uses _____ to help with the transfers when handling network interfaces. |
| A. | Input Buffer storage |
| B. | Signal echancers |
| C. | Bridge circuits |
| D. | All of the mentioned |
| Answer» B. Signal echancers | |
| 413. |
The technique where the controller is given complete access to main memory is |
| A. | Cycle stealing |
| B. | Memory stealing |
| C. | Memory Con |
| D. | Burst mode |
| Answer» E. | |
| 414. |
The controller is connected to the __ |
| A. | Processor BUS |
| B. | System BUS |
| C. | External BUS |
| D. | None of the mentioned |
| Answer» C. External BUS | |
| 415. |
After the complition of the DMA transfer the processor is notified by |
| A. | Acknowledge signal |
| B. | Interrupt signal |
| C. | WMFC signal |
| D. | None of the mentioned |
| Answer» C. WMFC signal | |
| 416. |
A privilege exception is raised |
| A. | When a process tries to change the mode of the system |
| B. | When a process tries to change the piority level of the other processes |
| C. | When a process tries to access the memory allocated to other user |
| D. | All of the mentioned |
| Answer» E. | |
| 417. |
How is a privilege exception dealt with? |
| A. | The program is alted and the system switches into supervisor mode and restarts the program execution |
| B. | The Program is stopped and removed from the queue |
| C. | The system switches the mode and starts the execution of a new process |
| D. | The system switches mode and runs the debugger |
| Answer» B. The Program is stopped and removed from the queue | |
| 418. |
The different modes of operation of a computer is |
| A. | User and System mode |
| B. | User and Supervisor mode |
| C. | Supervisor and Trace mode |
| D. | Supervisor, User and Trace mode |
| Answer» C. Supervisor and Trace mode | |
| 419. |
The instructions which can be run only supervisor mode are |
| A. | Non-privileged instructions |
| B. | System instructions |
| C. | Privileged instructions |
| D. | Exception instructions |
| Answer» D. Exception instructions | |
| 420. |
In trace mode of operation is _______ |
| A. | The program is interrupted after each detection |
| B. | The program will not be stopped and the errors are sorted out after the complete program is scanned |
| C. | There is no effect on the program, i.e the program is executed without rectification of errors |
| D. | The program is alted only at specific points |
| Answer» B. The program will not be stopped and the errors are sorted out after the complete program is scanned | |
| 421. |
___ is/are types of exceptions. |
| A. | Trap |
| B. | Interrupt |
| C. | System calls |
| D. | All of the mentioned |
| Answer» E. | |
| 422. |
Interrupts initiated by an instruction is called as __ |
| A. | Internal |
| B. | External |
| C. | Hardware |
| D. | Software |
| Answer» C. Hardware | |
| 423. |
The anded output of the bits of the interrupt register and the mask register are set as input of: |
| A. | Priority decoder |
| B. | Priority encoder |
| C. | Process id encoder |
| D. | Multiplexer |
| Answer» C. Process id encoder | |
| 424. |
_____ interrupt method uses register whose bits are set seperately by interrupt signal for each device. |
| A. | Parallel priority interrupt |
| B. | Serial priority interrupt |
| C. | Daisy chaining |
| D. | None of the mentioned |
| Answer» B. Serial priority interrupt | |
| 425. |
__ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt. |
| A. | Mass |
| B. | Mark |
| C. | Make |
| D. | Mask |
| Answer» E. | |
| 426. |
Which table handle stores the addresses of the interrupt handling sub-routines? |
| A. | Interrupt-vector table |
| B. | Vector table |
| C. | Symbol link table |
| D. | None of the mentioned |
| Answer» B. Vector table | |
| 427. |
________ method is used to establish priority by serially connecting all devices that request an interrupt. |
| A. | Vectored-interrupting |
| B. | Daisy chain |
| C. | Priority |
| D. | Polling |
| Answer» C. Priority | |
| 428. |
In daisy chaining device 0 will pass the signal only if it has _ |
| A. | Interrupt request |
| B. | No interrupt request |
| C. | Both No interrupt and Interrupt request |
| D. | None of the mentioned |
| Answer» C. Both No interrupt and Interrupt request | |
| 429. |
The processor indicates to the devices that it is ready to recieve interrupts __ |
| A. | By enabling the interrupt request line |
| B. | By enabling the IRQ bits |
| C. | By activating the interrupt acknowledge line |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 430. |
The starting address sent by the device in vectored interrupt is called as ___ |
| A. | Location id |
| B. | Interrupt vector |
| C. | Service location |
| D. | Service id |
| Answer» C. Service location | |
| 431. |
The code sent by the device in vectored interrupt is _____ long. |
| A. | upto 16 bits |
| B. | upto 32 bits |
| C. | upto 24 bits |
| D. | 4-8 bits |
| Answer» E. | |
| 432. |
In vectored interrupts, how does the device identify itself to the processor? |
| A. | By sending its device id |
| B. | By sending the machine code for the interrupt service routine |
| C. | By sending the starting address of the service routine |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 433. |
The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is ___ |
| A. | Polling |
| B. | Vectored interrupts |
| C. | Interrupt nesting |
| D. | Simultaneous requesting |
| Answer» C. Interrupt nesting | |
| 434. |
When dealing with multiple device interrupts, which mechanism is easy to implement? |
| A. | Polling method |
| B. | Vectored interrupts |
| C. | Interrupt nesting |
| D. | None of the mentioned |
| Answer» B. Vectored interrupts | |
| 435. |
CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged |
| A. | A hardware interrupt is needed |
| B. | A software interrupt is needed |
| C. | Either hardware or software interrupt is needed |
| D. | A non-privileged instruction (which does not generate an interrupt)is needed |
| Answer» C. Either hardware or software interrupt is needed | |
| 436. |
The 8085 microprocessor respond to the presence of an interrupt |
| A. | As soon as the trap pin becomes ‘LOW’ |
| B. | By checking the trap pin for ‘high’ status at the end of each instruction fetch |
| C. | By checking the trap pin for ‘high’ status at the end of execution of each instruction |
| D. | By checking the trap pin for ‘high’ status at regular intervals |
| Answer» D. By checking the trap pin for ‘high’ status at regular intervals | |
| 437. |
The resistor which is attached to the service line is called _ |
| A. | Push-down resistor |
| B. | Pull-up resistor |
| C. | Break down resistor |
| D. | Line resistor |
| Answer» C. Break down resistor | |
| 438. |
An interrupt that can be temporarily ignored is |
| A. | Vectored interrupt |
| B. | Non-maskable interrupt |
| C. | Maskable interrupt |
| D. | High priority interrupt |
| Answer» D. High priority interrupt | |
| 439. |
The signal sent to the device from the processor to the device after recieving an interrupt is |
| A. | Interrupt-acknowledge |
| B. | Return signal |
| C. | Service signal |
| D. | Permission signal |
| Answer» B. Return signal | |
| 440. |
The time between the recieval of an interrupt and its service is _____ |
| A. | Interrupt delay |
| B. | Interrupt latency |
| C. | Cycle time |
| D. | Switching time |
| Answer» C. Cycle time | |
| 441. |
The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is |
| A. | Exceptions |
| B. | Signal handling |
| C. | Interrupts |
| D. | DMA |
| Answer» D. DMA | |
| 442. |
The process where in the processor constantly checks the status flags is called as |
| A. | Polling |
| B. | Inspection |
| C. | Reviewing |
| D. | Echoing |
| Answer» B. Inspection | |
| 443. |
The method which offers higher speeds of I/O transfers is |
| A. | Interrupts |
| B. | Memory mapping |
| C. | Program-controlled I/O |
| D. | DMA |
| Answer» E. | |
| 444. |
To overcome the lag in the operating speeds of the I/O device and the processor we use |
| A. | BUffer spaces |
| B. | Status flags |
| C. | Interrupt signals |
| D. | Exceptions |
| Answer» C. Interrupt signals | |
| 445. |
The method of accessing the I/O devices by repeatedly checking the status flags is |
| A. | Program-controlled I/O |
| B. | Memory-mapped I/O |
| C. | I/O mapped |
| D. | None of the mentioned |
| Answer» B. Memory-mapped I/O | |
| 446. |
The system is notified of a read or write operation by |
| A. | Appending an extra bit of the address |
| B. | Enabling the read or write bits of the devices |
| C. | Raising an appropriate interrupt signal |
| D. | Sending a special signal along the BUS |
| Answer» E. | |
| 447. |
The advantage of I/O mapped devices to memory mapped is |
| A. | The former offers faster transfer of data |
| B. | The devices connected using I/O mapping have a bigger buffer space |
| C. | The devices have to deal with fewer address lines |
| D. | No advantage as such |
| Answer» D. No advantage as such | |
| 448. |
The usual BUS structure used to connect the I/O devices is |
| A. | Star BUS structure |
| B. | Multiple BUS structure |
| C. | Single BUS structure |
| D. | Node to Node BUS structure |
| Answer» D. Node to Node BUS structure | |
| 449. |
The sub-routine service procedure, is similar to that of the interrupt service routine in ______ |
| A. | Method of context switch |
| B. | Returning |
| C. | Process execution |
| D. | Method of context switch & Process execution |
| Answer» E. | |
| 450. |
In memory-mapped I/O _ |
| A. | The I/O devices and the memory share the same address space |
| B. | The I/O devices have a seperate address space |
| C. | The memory and I/O devices have an associated address space |
| D. | A part of the memory is specifically set aside for the I/O operation |
| Answer» B. The I/O devices have a seperate address space | |