MCQOPTIONS
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MCQOPTIONS
This section includes 585 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 251. |
The standard SRAM chips are costly as ____ |
| A. | They use highly advanced micro-electronic devices |
| B. | They house 6 transistor per chip |
| C. | They require specially designed PCB’s |
| D. | None of the mentioned |
| Answer» C. They require specially designed PCB’s | |
| 252. |
The memory module obtained by placing a number of flash chips for higher memory storage called as __ |
| A. | FIMM |
| B. | SIMM |
| C. | Flash card |
| D. | RIMM |
| Answer» D. RIMM | |
| 253. |
The disadvantage of the EEPROM is/are __ |
| A. | The requirement of different voltages to read,write and store information |
| B. | The requirement of different voltages to read,write and store information |
| C. | The inefficient memory mapping schemes used |
| D. | All of the mentioned |
| Answer» B. The requirement of different voltages to read,write and store information | |
| 254. |
The memory devices which are similar to EEPROM but differ in the cost effectiveness is _____ |
| A. | Memory sticks |
| B. | Blue-ray devices |
| C. | Flash memory |
| D. | CMOS |
| Answer» D. CMOS | |
| 255. |
The flash memories find application in ____ |
| A. | Super computers |
| B. | Mainframe systems |
| C. | Distributed systems |
| D. | Portable devices |
| Answer» E. | |
| 256. |
The contents of the EPROM are earsed by __ |
| A. | Overcharging the chip |
| B. | Exposing the chip to UV rays |
| C. | Exposing the chip to IR rays |
| D. | Discharging the Chip |
| Answer» C. Exposing the chip to IR rays | |
| 257. |
The RDRAM chips assembled into larger memory modules called ___ |
| A. | RRIM |
| B. | DIMM |
| C. | SIMM |
| D. | All of the mentioned |
| Answer» B. DIMM | |
| 258. |
The PROM is more effective than ROM chips in regard to ___ |
| A. | Cost |
| B. | Memory management |
| C. | Speed of operation |
| D. | Both Cost and Speed of operation |
| Answer» E. | |
| 259. |
The ROM chips are mainly used to store ____ |
| A. | System files |
| B. | Root directories |
| C. | Boot files |
| D. | Driver files |
| Answer» D. Driver files | |
| 260. |
The difference between the EPROM and ROM circuitory is _ |
| A. | The usage of MOSFET’s over transistors |
| B. | The usage of JFET’s over transistors |
| C. | The usage of an extra transistor |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 261. |
PROM stands for ______ |
| A. | Programmable Read Only Memory |
| B. | Pre-fed Read Only Memory |
| C. | Pre-required Read Only Memory |
| D. | Programmed Read Only Memory |
| Answer» B. Pre-fed Read Only Memory | |
| 262. |
A RAMBUS which has 18 data lines is called as ___ |
| A. | Extended RAMBUS |
| B. | Direct RAMBUS |
| C. | Direct RAMBUS |
| D. | Indirect RAMBUS |
| Answer» C. Direct RAMBUS | |
| 263. |
The type of signaling used in RAMBUS is __ |
| A. | CLK signalling |
| B. | Differential signalling |
| C. | Integral signalling |
| D. | None of the mentioned |
| Answer» C. Integral signalling | |
| 264. |
The data is transfered over the RAMBUS as _____ |
| A. | Packets |
| B. | Blocks |
| C. | Swing voltages |
| D. | Bits |
| Answer» D. Bits | |
| 265. |
The RAMBUS requires specially designed memory chips similar to ___ |
| A. | SRAM |
| B. | SDRAM |
| C. | DRAM |
| D. | DDRRAM |
| Answer» D. DDRRAM | |
| 266. |
The special communication used in RAMBUS are __ |
| A. | RAMBUS channel |
| B. | D-link |
| C. | Dial-up |
| D. | None of the mentioned |
| Answer» B. D-link | |
| 267. |
The key feature of the RAMBUS tech is ___ |
| A. | Greater memory utilisation |
| B. | Effeciency |
| C. | Speed of transfer |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 268. |
RamBUS is better than the other memory chips in terms of |
| A. | Efficiency |
| B. | Speed of operation |
| C. | Wider bandwidth |
| D. | All of the mentioned |
| Answer» C. Wider bandwidth | |
| 269. |
The higher order bits of the address are used to _ |
| A. | Specify the row address |
| B. | Specify the column address |
| C. | Input the CS |
| D. | None of the mentioned |
| Answer» B. Specify the column address | |
| 270. |
The RAS and CAS signals are provided by the __ |
| A. | Mode register |
| B. | CS |
| C. | Memory controller |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 271. |
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read opeartion. Then the refresh overhead of the chip is ____ |
| A. | 0.0021 |
| B. | 0.0038 |
| C. | 0.0064 |
| D. | 0.0128 |
| Answer» C. 0.0064 | |
| 272. |
The address lines multiplexing is done using __ |
| A. | MMU |
| B. | Memory controller unit |
| C. | Page table |
| D. | Overlay geberator |
| Answer» C. Page table | |
| 273. |
To organise large memory chips we make use of __ |
| A. | Integrated chips |
| B. | Upgraded hardware |
| C. | Memory modules |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 274. |
The SRAM’s are basically used as _ |
| A. | Registers |
| B. | Caches |
| C. | TLB |
| D. | Buffer |
| Answer» C. TLB | |
| 275. |
To improve the data retrieval rate |
| A. | The memory is divided into two banks |
| B. | The memory is divided into two banks |
| C. | The clock frequency is increased |
| D. | None of the mentioned |
| Answer» B. The memory is divided into two banks | |
| 276. |
The chip can be disabled or cut off from external connection using ___ |
| A. | Chip select |
| B. | LOCK |
| C. | ACPT |
| D. | RESET |
| Answer» B. LOCK | |
| 277. |
The time taken to transfer a word of data to or from the memory is called as ____ |
| A. | Access time |
| B. | Cycle time |
| C. | Memory latency |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 278. |
DDR SDRAM’s perform fster data transfer by |
| A. | Integrating the hardware |
| B. | Transfering on both edges |
| C. | Improving the clock speeds |
| D. | Increasing the bandwidth |
| Answer» C. Improving the clock speeds | |
| 279. |
The SDRAM performs operation on the ___ |
| A. | Rising edge of the clock |
| B. | Falling edge of the clock |
| C. | Middle state of the clock |
| D. | Transition state of the clock |
| Answer» B. Falling edge of the clock | |
| 280. |
The mode register is used to |
| A. | Select the row or column data transfer mode |
| B. | Select the mode of operation |
| C. | Select the mode of operation |
| D. | All of the mentioned |
| Answer» C. Select the mode of operation | |
| 281. |
The block transfer capability of the DRAM is called _____ |
| A. | Burst mdoe |
| B. | Block mode |
| C. | Fast page mode |
| D. | Fast frame mode |
| Answer» D. Fast frame mode | |
| 282. |
The difference in address and data connection between DRAM’s and SDRAM’s is |
| A. | The usage of more number of pins in SDRAM’s |
| B. | The requirement of more address lines in SDRAM’s |
| C. | The usage of buffer in SDRAM’s |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 283. |
The difference between DRAM’s and SDRAM’s is/are _ |
| A. | The DRAM’s will not use the master slave relationship in data transfer |
| B. | The SDRAM’s make use of clock |
| C. | The SDRAM’s are more power efficient |
| D. | None of the mentioned |
| Answer» E. | |
| 284. |
In order to read multiple bytes of a row at the same time, we make use of __ |
| A. | Latch |
| B. | Shift register |
| C. | Cache |
| D. | Memory extension |
| Answer» B. Shift register | |
| 285. |
To get the row address of the required data ______ is enabled. |
| A. | CAS |
| B. | RAS |
| C. | CS |
| D. | Sense/write |
| Answer» C. CS | |
| 286. |
The processor must take into account the delay in accessing the memory location, such memories are called _ |
| A. | Delay integrated |
| B. | Asynchronous memories |
| C. | Synchronous memories |
| D. | Isochronous memories |
| Answer» C. Synchronous memories | |
| 287. |
To reduce the number of external connections reqiured, we make use of __ |
| A. | De-multiplexer |
| B. | Multiplexer |
| C. | Encoder |
| D. | Decoder |
| Answer» C. Encoder | |
| 288. |
The disadvantage of DRAM over SRAM is/are __ |
| A. | Lower data storage capacities |
| B. | Higher heat descipation |
| C. | The cells are not static |
| D. | All of the mentioned |
| Answer» D. All of the mentioned | |
| 289. |
The Reason for the disregarding of the SRAM’s is ____ |
| A. | Low Efficiency |
| B. | High power consumption |
| C. | High power consumption |
| D. | All of the mentioned |
| Answer» D. All of the mentioned | |
| 290. |
The advantage of CMOS SRAM over the transistor one’s is ______ |
| A. | Low cost |
| B. | High efficiency |
| C. | High durability |
| D. | Low power consumption |
| Answer» E. | |
| 291. |
1024 X 1 |
| A. | Dynamic memory |
| B. | Static memory |
| C. | Register |
| D. | Cache |
| Answer» C. Register | |
| 292. |
A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organised into ___ |
| A. | 128 X 8 |
| B. | 256 X 4 |
| C. | 512 X 2 |
| D. | 1024 X 1 |
| Answer» E. | |
| 293. |
The number of external connections required in 16 X 8 memory organisation is |
| A. | 14 |
| B. | 19 |
| C. | 15 |
| D. | 12 |
| Answer» B. 19 | |
| 294. |
The word line is driven by the __ |
| A. | Chip select |
| B. | Address decoder |
| C. | Data line |
| D. | Control line |
| Answer» C. Data line | |
| 295. |
A 16 X 8 organisation of memory cells, can store upto __ |
| A. | 256 bits |
| B. | 1024 bits |
| C. | 512 bits |
| D. | 128 bits |
| Answer» E. | |
| 296. |
The cells in a row are connected to a common line called __ |
| A. | Work line |
| B. | Word line |
| C. | Length line |
| D. | Principle diagonal |
| Answer» C. Length line | |
| 297. |
VLSI stands for _____ |
| A. | Very Large Scale Integration |
| B. | Very Large Stand-alone Integration |
| C. | Volatile Layer System Interface |
| D. | None of the mentioned |
| Answer» B. Very Large Stand-alone Integration | |
| 298. |
The cells in each column are connected to __ |
| A. | Word line |
| B. | Data line |
| C. | Read line |
| D. | Sense/ Write line |
| Answer» E. | |
| 299. |
The logical addresses generated by the cpu are mapped onto physical memory by ___ |
| A. | Relocation register |
| B. | TLB |
| C. | MMU |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 300. |
________ is the bootleneck, when it comes computer performance. |
| A. | Memory access time |
| B. | Memory cycle time |
| C. | Delay |
| D. | Latency |
| Answer» C. Delay | |