MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 585 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The instruction used to cause unconditional jump is __ |
| A. | UJG |
| B. | JG |
| C. | JMP |
| D. | GOTO |
| Answer» D. GOTO | |
| 2. |
The IA-32 system follows _____ design. |
| A. | RISC |
| B. | CISC |
| C. | SIMD |
| D. | None of the mentioned |
| Answer» C. SIMD | |
| 3. |
data directive is used ______ |
| A. | To indicate the ending of the data section |
| B. | To indicate the beginning of the data section |
| C. | To declare all the source operands |
| D. | To Initialize the operands |
| Answer» C. To declare all the source operands | |
| 4. |
___ instruction is used to check the bit of the condition flags. |
| A. | TEST |
| B. | TB |
| C. | CHECK |
| D. | BT |
| Answer» E. | |
| 5. |
The bit present in the op code, indicating which of the operands is the source is called as ____ |
| A. | SRC bit |
| B. | Indirection bit |
| C. | Direction bit |
| D. | FRM bit |
| Answer» D. FRM bit | |
| 6. |
The division operation in IA-32 is a single operand instruction so it is assumed that _____ |
| A. | The divisor is stored in the EAX register |
| B. | The dividend is stored in the EAC register |
| C. | The divisor is stored in the accumulator |
| D. | The dividend is stored in the accumulator |
| Answer» B. The dividend is stored in the EAC register | |
| 7. |
The MMX (Multimedia Extension) operands are stored in ___ |
| A. | General purpose registers |
| B. | Banked registers |
| C. | Float point registers |
| D. | Graphic registers |
| Answer» D. Graphic registers | |
| 8. |
In case of multimedia extension instructions the pixels are encoded into a data item of _____ |
| A. | 16 bit |
| B. | 32 bit |
| C. | 24 bit |
| D. | 8 bit |
| Answer» E. | |
| 9. |
Which architecture is suitable for a wide range of data types ? |
| A. | ARM |
| B. | 68000 |
| C. | IA-32 |
| D. | ASUS firebird |
| Answer» D. ASUS firebird | |
| 10. |
The IA-32 system follows _____ design . |
| A. | RISC |
| B. | CISC |
| C. | SIMD |
| D. | None of the mentioned |
| Answer» C. SIMD | |
| 11. |
The instruction used to multiply operands yielding a double integer outcome is _ |
| A. | MUL |
| B. | IMUL |
| C. | DMUL |
| D. | EMUL |
| Answer» C. DMUL | |
| 12. |
REPINS instruction is used to ____ |
| A. | Transfer a block of data serially from Input device to the processor |
| B. | Transfer a block of data parallely from Input device to the processor |
| C. | Transfer a block of data serially from Input device to the ouput device |
| D. | Transfer a block of data parallely from Input device to the output device |
| Answer» C. Transfer a block of data serially from Input device to the ouput device | |
| 13. |
SIMD stands for ____ |
| A. | Single Instruction Multiple Data |
| B. | Simple Instruction Multiple Decoding |
| C. | Sequential Instruction Multiple Decoding |
| D. | System Information Mutable Data |
| Answer» B. Simple Instruction Multiple Decoding | |
| 14. |
____ instruction is used to check the bit of the condition flags. |
| A. | TEST |
| B. | TB |
| C. | CHECK |
| D. | BT |
| Answer» E. | |
| 15. |
The ____ directive is used to allocate 4 byte of memory. |
| A. | DD |
| B. | ALLOC |
| C. | RESERVE |
| D. | SPACE |
| Answer» B. ALLOC | |
| 16. |
The instructions of IA-32 machines are of length up to __ |
| A. | 4 bytes |
| B. | 8 bytes |
| C. | 16 bytes |
| D. | 2 bytes |
| Answer» E. | |
| 17. |
The instruction used to cause unconditional jump is ___ |
| A. | UJG |
| B. | JG |
| C. | JMP |
| D. | GOTO |
| Answer» D. GOTO | |
| 18. |
data directive is used ___ |
| A. | To indicate the ending of the data section |
| B. | To indicate the beginning of the data section |
| C. | To declare all the source operands |
| D. | To Initialize the operands |
| Answer» C. To declare all the source operands | |
| 19. |
The bit present in the op code, indicating which of the operands is the source is called as ______ |
| A. | SRC bit |
| B. | Indirection bit |
| C. | Direction bit |
| D. | FRM bit |
| Answer» D. FRM bit | |
| 20. |
The LEA mnemonic is used to ____ |
| A. | Load the effective address of an instruction |
| B. | Load the values of operands onto a accumulator |
| C. | declare the values as global constants |
| D. | Store the outcome of the operation at a memory location |
| Answer» B. Load the values of operands onto a accumulator | |
| 21. |
The instruction JG loop , does |
| A. | jumps to the memory location loop if the result of the most recent arithmetic op is even |
| B. | jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0 |
| C. | jumps to the memory location loop if the test condition is satisfied with the value of loop |
| D. | none of the mentioned |
| Answer» C. jumps to the memory location loop if the test condition is satisfied with the value of loop | |
| 22. |
The Bit extension of the register is denoted with the help of ____ symbol. |
| A. | $ |
| B. | ` |
| C. | E |
| D. | ~ |
| Answer» D. ~ | |
| 23. |
The register used to serve as PC is called as _____ |
| A. | Indirection register |
| B. | Instruction pointer |
| C. | R-32 |
| D. | None of the mentioned |
| Answer» C. R-32 | |
| 24. |
The The Floating point registers of IA-32 can operate on operands up to __ |
| A. | 128 bit |
| B. | 256 bit |
| C. | 80 bit |
| D. | 64 bit |
| Answer» E. | |
| 25. |
IOPL stands for ___ |
| A. | Input/Output Privilege level |
| B. | Input Output Process Link |
| C. | Internal Output Process Link |
| D. | Internal Offset Privilege Level |
| Answer» B. Input Output Process Link | |
| 26. |
In IA-32 architecture along with the general flags, the other conditional flags provided are _____ |
| A. | IOPL |
| B. | IF |
| C. | TF |
| D. | All of the mentioned |
| Answer» E. | |
| 27. |
The size of the floating registers can be extended upto __ |
| A. | 128 bit |
| B. | 256 bit |
| C. | 80 bit |
| D. | 64 bit |
| Answer» D. 64 bit | |
| 28. |
The addressing method used in IA-32 is _ |
| A. | Little Endian |
| B. | Big Endian |
| C. | X-Little Endian |
| D. | Both Little and Big Endian |
| Answer» B. Big Endian | |
| 29. |
____ directives are used to initialize operands. |
| A. | INT |
| B. | DATAWORD |
| C. | RESERVE |
| D. | DCD |
| Answer» E. | |
| 30. |
THe pseudo instruction used to load address into the register is _____ |
| A. | LOAD |
| B. | ADR |
| C. | ASSIGN |
| D. | PSLOAD |
| Answer» C. ASSIGN | |
| 31. |
_____ directive is used to name the register used for execution of an instruction. |
| A. | ASSIGN |
| B. | RN |
| C. | NAME |
| D. | DECLARE |
| Answer» C. NAME | |
| 32. |
____ directive specifies the start of the execution. |
| A. | START |
| B. | ENTRY |
| C. | MAIN |
| D. | ORIGIN |
| Answer» C. MAIN | |
| 33. |
___ directive is used indicate the beginning of the program instruction or data. |
| A. | EQU |
| B. | START |
| C. | AREA |
| D. | SPACE |
| Answer» D. SPACE | |
| 34. |
The offset used in the conditional branching is ____ bit. |
| A. | 24 |
| B. | 32 |
| C. | 16 |
| D. | 8 |
| Answer» B. 32 | |
| 35. |
The condition to check whether the branch should happen or not is given by _____ |
| A. | The lower order 8 bits of the instruction |
| B. | The higher order 4 bits of the instruction |
| C. | The lower order 4 bits of the instruction |
| D. | The higher order 8 bits of the instruction |
| Answer» C. The lower order 4 bits of the instruction | |
| 36. |
The BEQ instructions is used _ |
| A. | To check the equality condition between the operands and then branch |
| B. | To check if the Operand is greater than the condition value and then branch |
| C. | To check if the flag Z is set to 1 and then causes branch |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 37. |
____ instruction is used to get the 1’s compliment of the operand. |
| A. | COMP |
| B. | BIC |
| C. | ~CMP |
| D. | MVN |
| Answer» E. | |
| 38. |
The ability to shift or rotate in the same instruction along with other operation is performed with the help of _ |
| A. | Switching circuit |
| B. | Barrel switcher circuit |
| C. | Integrated Switching circuit |
| D. | Multiplexer circuit |
| Answer» C. Integrated Switching circuit | |
| 39. |
The Instruction, LDM R10!, {R0,R1,R6,R7} _ |
| A. | Loads the contents of R10 into R1,R0,R6 and R7 |
| B. | Creates a copy of the contents of R10 in the other registers except the above mentioned ones |
| C. | Loads the contents of the registers R1,R0,R6 and R7 to R10 |
| D. | Writes the contents of R10 into the above mentioned registers and clears R10 |
| Answer» B. Creates a copy of the contents of R10 in the other registers except the above mentioned ones | |
| 40. |
The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is _____ |
| A. | EA = [Rn]. |
| B. | EA = [Rn + Rm]. |
| C. | EA = [Rn] + Rm |
| D. | EA = [Rm] + Rn |
| Answer» B. EA = [Rn + Rm]. | |
| 41. |
The instructions which are used to load or store multiple operands are called as _ |
| A. | Banked instructions |
| B. | Lump transfer instructions |
| C. | Block transfer instructions |
| D. | DMA instructions |
| Answer» D. DMA instructions | |
| 42. |
___ symbol is used to signify write back mode. |
| A. | # |
| B. | ^ |
| C. | & |
| D. | ! |
| Answer» E. | |
| 43. |
The addressing mode where the EA of the operand is the contents of Rn is __ |
| A. | Pre-indexed mode |
| B. | Pre-indexed with write back mode |
| C. | Post-indexed mode |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 44. |
The banked registers are used for _____ |
| A. | Switching between supervisor and interrupt mode |
| B. | Extended storing |
| C. | Same as other general purpose registers |
| D. | None of the mentioned |
| Answer» B. Extended storing | |
| 45. |
RISC stands for ____ |
| A. | Restricted Instruction Sequencing Computer |
| B. | Restricted Instruction Sequential Compiler |
| C. | Reduced Instruction Set Computer |
| D. | Reduced Induction Set Computer |
| Answer» D. Reduced Induction Set Computer | |
| 46. |
In ARM, PC is implemented using __ |
| A. | Caches |
| B. | Heaps |
| C. | General purpose register |
| D. | Stack |
| Answer» D. Stack | |
| 47. |
The additional duplicate register used in ARM machines are called as __ |
| A. | Copied-registers |
| B. | Banked registers |
| C. | EXtra registers |
| D. | Extential registers |
| Answer» C. EXtra registers | |
| 48. |
ARM processors where basically designed for __ |
| A. | Main frame systems |
| B. | Distributed systems |
| C. | Mobile systems |
| D. | Super computers |
| Answer» D. Super computers | |
| 49. |
The address system supported by ARM systems is/are __ |
| A. | Little Endian |
| B. | Big Endian |
| C. | X-Little Endian |
| D. | Both Little & Big Endian |
| Answer» E. | |
| 50. |
ARM stands for ____ |
| A. | Advanced Rate Machines |
| B. | Advanced RISC Machines |
| C. | Artificial Running Machines |
| D. | Aviary Running Machines |
| Answer» C. Artificial Running Machines | |