Which of the following is responsible for coordinating various operatings using timing signals

Which of the following is responsible for coordinating various opera

1.	Which  of the following is responsible for coordinating various operatings using timing signals
A.	ALU
B.	control unit
C.	memory unit
D.	I/O unit
Answer» C. memory unit

Discussion

No Comment Found

Related MCQs

The value of the ratio M 1/M2 is 
The value of M1 is 
The valu of h2 is 
The value of h 1is 
Consider a new instruction named branch -on- bit -set (mnemonic bbs ).The instruction bbs reg pos label jumps to label if bit in position pos of register operand reg is one A register is 32 bits wide and the bits are numbered 0 to 31 bit in the following emuationof this instruction on a processor that does not have bbs implemented  temp -----reg and mask  Branch to label if temp is non -zero The variable temp is a temporary register For ocrrect emulation the variable mask must be generated by 
A CPU has five -stage pipeline and runs at 1 GHz frequency Instrution fetch happens in the first stage of the pipeline A conditional branch instruction  computer the target address and evaluates the processor branch until the branch outcome is known A program executes 10 9 instructions out of which 20 %are conditional branches If each instruction takes one cycle to complete on average then total execution time of the program is 
A CPU has a cache with block size 64 bytes The main memory has K banks each bank bank being c bytes wide consecutive c byte chunks are mapped on consecutiv banks with warp -around All the k banks can be accssed in parallel but tow accesses to the same bank must be serialized A cache block access may involve multiple iterations of parallel Each Iteration requires decoding the bank number s to be accessed in parallel and this takes k /2 ns . the latency of one bank access is 80 ns If c = 2 and k = 24 then latency of retrieving a cache block starting at address zero from main memory is 
In a memory system four 256x8 PROM chips are used to make total memory of size 1024x4 what is the number of address bus lines 
If each address space represents one byte of storage space how many address lines are needed to access RAM chip arranged in a 4x6 arryay where each chip is 8Kx4bits 
How many RAM chips of size (256KX1 bit) are required to build 1M Byte memory

Which&nbsp; of the following is responsible for coordinating various operatings using timing signals&nbsp;

Discussion

No Comment Found

Related MCQs

Reply to Comment

Which of the following is responsible for coordinating various operatings using timing signals