Which of the following is not a stage of pipeline of a RISC processor? – McqOptions

MCQOPTIONS

1.	Which of the following is not a stage of pipeline of a RISC processor?
A.	read registers and decode the instructions
B.	fetch instructions from registers
C.	write result into a register
D.	access an operand in data memory
Answer» C. write result into a register

Discussion

No Comment Found

Related MCQs

Parallel programs: Which speedup could be achieved according to Amdahl´s law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?
All deadlocks involve conflicting needs for __________
______________ sent to false and continue in the loop.
A situation where several processes access and manipulate the same data concurrently and the outcome of the execution depends on the particular order in which access takes place is called:
Each node of the tree has an_________________ , that is, the cost of the partialtour.
During the execution of the instructions, a copy of the instructions isplaced in the ______ .
The ____________ directive ensures that a specific memory location is updated atomically, rather than exposing it to the possibility of multiple, simultaneous writing threads.
What are the scoping clauses in OpenMP _________
The ____________is implemented more efficiently than a general parallelregion containing possibly several loops.
The processes exchange partial results instead of using onewaycommunications. Such a communication pattern is sometimes called a ___________.