What is the deadlock condition in VHDL? – McqOptions

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1.	What is the deadlock condition in VHDL?
A.	When WAIT statement keeps on waiting forever
B.	When WAIT UNTIL statement uses more than one signal
C.	When WAIT ON statement has only one signal
D.	When WAIT FOR statement doesn‚Äö√Ñ√∂‚àö√ë‚àö¬•t have any time clause
Answer» B. When WAIT UNTIL statement uses more than one signal

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