MCQOPTIONS
Home
About Us
Contact Us
Bookmark
Saved Bookmarks
Testing Subject
General Aptitude
Logical and Verbal Reasoning
English Skills Ability
Technical Programming
Current Affairs
General Knowledge
Finance & Accounting
GATE (Mechanical Engineering)
Chemical Engineering
→
Digital Circuits
→
Number System
→
Three cascaded decade counters will divide the inp...
1.
Three cascaded decade counters will divide the input frequency by
A.
10
B.
20
C.
100
D.
1000
Answer» E.
Show Answer
Discussion
No Comment Found
Post Comment
Related MCQs
A principle regarding most display decoders is that when the correct input is present, the related output will switch ____________
A 4-bit counter has a maximum modulus of ____________
Three cascaded decade counters will divide the input frequency by ____________
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________
An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is ____________
How many different states does a 3-bit asynchronous counter have?
The terminal count of a typical modulus-10 binary counter is ____________
What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
Internal propagation delay of asynchronous counter is removed by ____________
Reply to Comment
×
Name
*
Email
*
Comment
*
Submit Reply
Your experience on this site will be improved by allowing cookies. Read
Cookie Policy
Reject
Allow cookies