In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input conditions is: P = Q = ‘0’. If the input conditions is changed simultaneously to P = Q = ‘1’, the outputs X and Y are

either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’

either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’

In the latch circuit shown, the NAND gates have non-zero, but unequal

1.	In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input conditions is: P = Q = ‘0’. If the input conditions is changed simultaneously to P = Q = ‘1’, the outputs X and Y are
A.	X = ‘1’, Y = ‘1’
B.	either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’
C.	either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’
D.	X = ‘0’, Y = ‘0’
Answer» C. either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’

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In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input conditions is: P = Q = ‘0’. If the input conditions is changed simultaneously to P = Q = ‘1’, the outputs X and Y are

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