A state diagram of a logic gate which exhibits delay in the output is shown in the figure, where X is the don’t care condition and Q is the output representing the stateThe logic gate represented by the state diagram is

A state diagram of a logic gate which exhibits delay in the output is

1.	A state diagram of a logic gate which exhibits delay in the output is shown in the figure, where X is the don’t care condition and Q is the output representing the stateThe logic gate represented by the state diagram is
A.	XOR gate
B.	OR gate
C.	AND gate
D.	NAND gate
Answer» E.

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A state diagram of a logic gate which exhibits delay in the output is shown in the figure, where X is the don’t care condition and Q is the output representing the stateThe logic gate represented by the state diagram is

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