1.

A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q0 Q1 Q2 = 101. The frequency of output Q0 Q1 Q2 will be

A. <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/37-540-1.png">
B. <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/37-540-2.png">
C. <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/37-540-3.png">
D. <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/37-540-4.png">
Answer» D. <img src="/_files/images/electronics-and-communication-engineering/digital-electronics/37-540-4.png">


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